Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2000-09-27
2002-04-23
Bowers, Charles (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S426000, C438S434000
Reexamination Certificate
active
06376331
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a plurality of elements and isolation regions for isolating these elements on a substrate, and more specifically, it relates to a semiconductor device in which element isolation regions are formed by digging trenches on a semiconductor substrate and filling these trenches with an insulating film, and a method for manufacturing the semiconductor device.
2. Description of the Prior Art
As a technique for the mutual isolation of elements formed on a semiconductor substrate in a semiconductor device, there has been used a method which comprises isolating the elements from each other by digging trenches between element regions on the semiconductor substrate, and filling these trenches with an insulating film (hereinafter referred to simply as “the trench isolation”). This trench isolation is a very useful technique for the mutual isolation of the elements in the finely highly integrated semiconductor device, because the size of the semiconductor device depends on the precisely formed trenches on the semiconductor substrate.
However, when a voltage is applied to a gate electrode, an electric field is concentrated along an element region top surface edges on the semiconductor substrate under the gate electrodes, so that a parasitic channels having a lower gate voltage than an original threshold voltage are formed in these portions. In consequence, a problem that a leak current increases in an OFF state tends to take place.
As a technique for solving this problem, there are known methods described in Japanese Patent Application Laid-open Nos. 92549/1984 and 54641/1986, and in Japanese Patent publication (Kokoku) No. 54468/1991. That is to say, according to these methods, the same conductive type impurity as in the substrate is introduced into surfaces of the semiconductor substrate that are in contact with an insulating film in element isolation regions to heighten the concentration of the impurity therein, whereby the formation of the parasitic channels is prevented.
One example of these conventional methods will be described with reference to drawings. A semiconductor device having the conventional trench isolation is shown in FIGS.
4
(
a
) to
4
(
c
). In FIG.
4
(
a
), a part of the semiconductor device is seen from above the element top surface, and an element region
10
is constituted of a source region
12
, a gate electrode
14
and a drain region
16
, and this element region is isolated from another element by an element isolation region
18
. FIG.
4
(
b
) is a cross-sectional view of the gate electrode
14
cut along the line
4
(
b
)-
4
(
b
) in FIG.
4
(
a
), and FIG.
4
(
c
) is a cross-sectional view of the drain region
16
cut along the line
4
(
b
)-
4
(
b
) in FIG.
4
(
a
).
In the cross-section along the line
4
(
b
)-
4
(
b
), as shown in FIG.
4
(
b
), a gate insulating film
22
and the gate electrode
14
are disposed on the element region
10
on a first conductive type semiconductor substrate
20
, and the element region
10
is isolated from another element by the element isolation region
18
which is formed by digging a trench on the semiconductor substrate
20
and filling the trench with the insulating film. That is to say, the element region
10
has a substantially flat top surface and comes in contact with the element isolation regions near element region top surface edges
26
. A side surface
28
of the element region is a vertical or an inclined wall surface extending from the top surface edge of the element region and the bottom of the trench and comes in contact with the insulating film in the element isolation region
18
.
In this conventional example, when a voltage is applied to the gate electrode
14
, the concentration of an electric field occurs along the element region top surface edges
26
under the gate electrode
14
, generating a parasitic channel. As a means to solve this problem the concentration of the first conductive type impurity in substrate surfaces
29
which are in contact with the bottom of the element isolation region
18
, the element region side surface
28
and the element region top surface edge
26
is set so as to be higher than in the body of the element region.
Furthermore, in the cross-section along the line
4
(
c
)-
4
(
c
), as shown in FIG.
4
(
c
), the drain region
16
containing a second conductive type impurity is formed on the semiconductor substrate surface in the element region
10
, and this element region
10
is isolated from another element by the element isolation region
18
formed by digging the trench on the semiconductor substrate
20
and filling the trench with the insulating film. In the substrate surface
24
which is in contact with the trench bottom of the element isolation region
18
and a portion of the element region side under the drain region
16
, the first conductive type impurity is present at a higher concentration than in the body of the element region. Incidentally, in
FIG. 4
, wires and the like on the shown element are omitted to avoid complexity.
FIGS.
5
(
a
) to
5
(
e
) show a cross-section along the line
4
(
b
)-
4
(
c
) in FIG.
4
(
a
) which explains a manufacturing method of the semiconductor device having such a conventional trench isolation as shown in FIG.
4
.
As shown in FIG.
5
(
a
), a silicon oxide film
30
is formed on a first conductive type silicon substrate (a semiconductor substrate)
20
, and additionally, on the silicon oxide film
30
, for example, an aluminum film (a mask material)
32
having a thickness of 0.5 &mgr;m is formed, followed by forming a mask comprising the aluminum film
32
and a resist film
34
by lithography. Next, as shown in FIG.
5
(
b
), the semiconductor substrate
20
is subjected to anisotropic etching through the above-mentioned mask to form trenches
36
for element isolation regions having a depth of about 0.6 &mgr;m.
In succession, as shown in FIG.
5
(
c
), the side walls of the aluminum film
32
are partially etched by isotropic etching so that the aluminum film
32
may retract as much as about 0.1 &mgr;m.
As shown in FIG.
5
(
d
), the resist film
34
for the mask is peeled off, and the first conductive type impurity is then implanted into the semiconductor substrate
20
by using the retracted aluminum film
32
as a mask, a dose of the impurity being, for example, 3×10
12
cm
−2
ions. At this time, the ion is implanted into the bottoms and the sides of the trenches
36
for the isolation regions as well as the element region top surface edge
26
which is not masked with the aluminum film
32
.
Next, as shown in FIG.
5
(
e
), the trenches
36
for the element isolation regions are filled with, for example, a CVD silicon oxide film (an insulating film). The above-mentioned aluminum film
32
is removed, and the surfaces of the filled isolation regions are flattened. In succession, a usual procedure is carried out to form the gate oxide film
22
and the gate electrode
14
shown in FIG.
4
. Furthermore, the second conductive type impurity is ion-implanted, thereby forming the source region
12
and the drain region
16
, whereby a semiconductor device having the trench isolation is completed.
However, in the conventional technique, on the side of the element region as shown in FIG.
4
(
c
), the drain region
16
containing the second conductive type impurity is in contact with the side surface containing the first conductive type impurity at a high concentration, and therefore some problems are present. For example, a junction capacitance increases and retards the driving velocity of the elements, and a junction leak current increases inconveniently.
In particular, with the progress of high integration through the formation of fine elements, in the semiconductor integrated circuit apparatus in which a semiconductor device having a trench isolation is used, the total peripheral length of the element regions per chip increases, so that junctions having a high impurity concentrat
Bowers Charles
Foley & Lardner
Kebede Brook
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