Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
2000-02-17
2001-11-27
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C438S106000, C438S110000, C438S114000, C438S127000, C438S458000, C438S462000
Reexamination Certificate
active
06323061
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and to a method for manufacturing a semiconductor device, and more particularly it relates to a compact, thin semiconductor device, and to a method of manufacturing a semiconductor device with high productivity.
2. Background of the Invention
In recent years, in response to the demand for electronic equipment with sophisticated functions, compactness, lightweight, and high speed, a variety of forms of semiconductor devices are being developed. For example, this is not even limited to integrated circuits, there being a demand for compactness and light weight in such discrete components as diodes and transistors as well.
For example, in a transistor of the past, there has been a configuration in which electrodes for outputting signals have been provided on a main surface and other electrodes have been provided on a surface that is opposite the main surface of the chip
1
. In contrast to this approach, in response to recent demand for compactness in semiconductor devices, there have been attempts to achieve compactness by providing a plurality of electrodes on a single surface of the semiconductor chip.
FIG. 5
shows a cross-section view of a transistor of the past which has a plurality of electrodes on a single surface of the semiconductor chip. In this semiconductor device of the past, as shown in
FIG. 5
, on one surface of a semiconductor chip
1
are provided a gate electrode (or base electrode)
41
, a source electrode (or emitter electrode)
42
, and a drain electrode (or collector electrode)
43
.
In a transistor such as shown in
FIG. 5
, however, the following problem occurs.
In general, a transistor has characteristics such that, by applying a voltage to the gate electrode, the value of resistance between the drain electrode and the source electrode is reduced (this resistance value being referred to hereinafter as the on resistance). In this case, in order to cause a prescribed current to flow in the drain electrode, a voltage is applied to the drain electrode, this being smaller the smaller the on resistance is. While the power consumption of each transistor is not that large, because a large number of such transistors are provided in the circuit product, it is desirable that the power consumption of each transistor be made smaller. That is, because the power consumed to drive a transistor is smaller the smaller the on resistance is, it is desirable to make the on resistance of the transistor small.
The resistance value r of an electrode is generally determined as p=l/S (where p is the resistivity, l is the length of the electrode, and S is the cross-sectional area). In a semiconductor device of the past such as shown in
FIG. 5
, if the width W′ of the drain electrode
43
is made larger, the resistance value r, which is the on resistance, becomes smaller. However, the drain electrode
43
is formed of a semiconductor substance formed by a diffusion process as described above, the only way to make the cross-sectional area, or the width W′ of the drain electrode
43
large, is to make the semiconductor chip
1
larger. That is, in a semiconductor device of the past such as shown in
FIG. 5
, it is not possible to make the semiconductor chip itself small and obtain a sufficiently large on resistance. Thus, in a conventional semiconductor device, in the case in which the drain electrode and the source electrode are formed on one and the same surface and in which a drain electrode is formed in proximity to the gate electrode and source electrode, there was the problem of not being able to achieve a small enough overall size.
Accordingly, it is an object of the present invention to solve the above-noted problem in the prior art, by providing a compact, thin semiconductor device. It is a further object of the present invention to provide a method for manufacturing a semiconductor device featuring good productivity.
SUMMARY OF THE INVENTION
In order to achieve the above-noted objects, the first aspect of the present invention is a semiconductor device comprising, a semiconductor chip having a first electrode on a main surface thereof, a second electrode made of a conductive resin electrode having a base portion in contact with a surface opposite to the main surface of the semiconductor chip, and a side portion extended from one end portion of the base portion in the direction toward the main surface of the semiconductor chip, and an end part of the side portion of the second electrode is provided over the main surface of the semiconductor chip.
In the present invention, the second electrode has a bending part formed between the base portion and the side portion at a substantially right angle.
In the present invention, the side portion of the second electrode is provided between a first insulating resin which seals at least the main surface of the semiconductor chip and a second insulating resin which seals surfaces other than the main surface of the semiconductor chip.
In the present invention, the side portion of the second electrode is provided along one side surface of the semiconductor chip.
The second aspect of the present invention is a method of manufacturing a semiconductor device comprising; a first step of forming a plurality of first electrodes
10
(
11
,
12
) on a main surface
0
a
of a semiconductor wafer
0
, a second step of affixing the semiconductor wafer
0
, to a first tape
29
so that the first electrodes
10
are facing up, a third step of dicing the semiconductor wafer
0
in one direction along A-A′ in FIG.
2
(
c
), so as to form a plurality of semiconductor units
111
having a plurality of semiconductor chips
1
, a fourth step of expanding width of first grooves
30
that are formed when the dicing in the third step is performed, a fifth step of orienting the plurality of semiconductor units
111
so that surfaces
1
a
on which the first electrodes
10
are provided are facing up, and arranging the plurality of semiconductor units
111
on a flat sheet
31
so as to form second grooves
18
, a sixth step of covering surfaces
1
a
of the semiconductor units
111
and burying the second groove
18
with an insulating resin
14
and hardening the insulating resin
14
, a seventh step of affixing the semiconductor units
111
to a second tape
32
so that the first electrodes
10
are facing down, an eighth step of dicing the semiconductor formed in the sixth step in a direction parallel to the second groove
18
, at substantially the center of said second groove
18
, so as to form third grooves
33
, a ninth step of covering the semiconductor formed in the eighth step and burying the third grooves
33
with a conductive resin
16
, a tenth step of dicing the semiconductor formed in the ninth step along boundaries formed between the conductive resin
16
and the insulating resin
14
so as to form second electrodes
13
, an eleventh step of dicing the semiconductor formed in the tenth step in a direction perpendicular to the boundaries, so as to form a plurality of semiconductor devices
19
having the first electrode
10
and the second electrode
13
, and forming fourth grooves
34
between the semiconductor devices
19
, a twelfth step of expanding the fourth grooves
34
, a thirteenth step of covering the semiconductor devices
19
formed in the eleventh step with an insulating resin
15
, and burying the fourth grooves
34
with the insulating resin
15
, and hardening the insulating resin
15
, and a fourteenth step of dicing to form separate semiconductor devices
4
having a prescribed number of the semiconductor chips
1
.
REFERENCES:
patent: 6019523 (2000-01-01), Honmou
patent: 6049121 (2000-04-01), Toyosawa et al.
patent: 6184109 (2001-02-01), Sasaki et al.
Sakazaki Atsushi
Yoshitake Tomonobu
Bowers Charles
Geyer Scott B.
NEC Corporation
Young & Thompson
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