Semiconductor device manufacturing: process – Making passive device – Trench capacitor
Reexamination Certificate
1999-05-24
2001-10-23
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making passive device
Trench capacitor
C438S138000, C438S243000, C438S455000
Reexamination Certificate
active
06306719
ABSTRACT:
The present application claims priority from Korean Application No. 20723/93 filed Oct. 7, 1993, the entire disclosure of which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the same. More particularly, the present invention relates to a semiconductor device which enables increased integration, and a method for manufacturing the same.
Integrating the maximum number of devices in the minimum cell area is important for increasing the integration of a semiconductor memory cell, and particularly, of a dynamic random access memory (DRAM) cell.
In a next-generation 1 Gb DRAM, the memory cell composed of one transistor and one capacitor occupies an area of 0.3 &mgr;m
2
or less. This is the same area as previously needed for just the contact hole for interconnection in a one mega-bit DRAM cell. Forming one transistor; one capacitor, and one contact hole for interconnection all together in such a small area to form a unit cell, is practically impossible with current technology. Particularly, current layout methods have reached a bottleneck in terms of area limitation, so that a novel scheme for achieving the above has become necessary.
In most memory cells now incorporated in chips, a transistor, a capacitor and a contact hole are formed laterally on a planar layout, and the total area thereof acts as a factor in determining the area of the memory cell. Accordingly, since a transistor, a capacitor, and a contact hole for connection of the source and drain regions are formed in an area of 0.3 &mgr;m
2
or less for constituting a giga-bit memory cell, a three-dimensional cell structure is needed to overcome area limitations, and the cell structure must be altered from a lateral layout structure into a vertical layout structure.
While there exists a trench structure or a stacked structure as a typical example of such a three-dimensional cell structure, these structures cannot satisfy a capacitance requirement for next-generation devices.
T. Ozaki el al. suggest a SIMPLE cell wherein the capacitor area can be increased while an isolation region area is minimized (see
IEDM '
91, “A Surrounding Isolation-merged Plate Electrode (SIMPLE) Cell with Checkered Layout for 256 Mbit DRAMs and Beyond”). However, since the process for connecting the source region of a transistor with a capacitor's storage-node in the SIMPLE cell is a lateral scheme, a contact hole area for connection is needed. Also, a contact hole area for connecting a drain region with a bit-line is needed. Therefore, according to the SIMPLE cell structure, though a design rule of 0.1 &mgr;m is used, unit DRAM elements cannot be formed within an area of 0.3 &mgr;m
2
, and thus, forming the memory cell for giga bit DRAMs and beyond is impossible.
K. Sunouchi et al. suggest a SGT cell wherein all the devices for the unit memory cell are formed in one silicon pillar isolated by a matrix-like trench (see
IEDM '
89, “A Surrounding Gate Transistor (SGT) cell for 64 and 256 Mbit DRAMs”). However, in the SGT cell, a process for connecting a word-line is added, and the process of forming the silicon pillar and capacitor are complex. Also, the isolation characteristics between the memory cells are poor, and there is a high possibility that a short between a capacitor plate-node and a gate electrode will occur during a process for forming the gate electrode.
Also, U.S. Pat. No. 4,833,516 discloses a memory cell having a transistor and a capacitor of vertical structure. However, such a memory cell has reduced efficiency in terms of cell area utilization.
Further, Toshiyuki Nishihara et al. suggest a silicon-on-insulator (SOI) structure cell wherein a capacitor is completely buried under a silicon layer, so that a memory cell area can be maximized (see
IEDM '
92, “A Buried Capacitor DRAM Cell with Bonded SOI for 256 M and 1 Gbit DRAMs”). However, in the SOI structure cell, it is difficult to control the remaining thickness during the process for polishing a silicon substrate, and a bit-line contact hole area for connecting the drain region of a transistor with a bit-line is needed.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a semiconductor device which solves the above problems of the conventional method and enables increased integration.
It is another object of the present invention to provide a method especially suited to manufacture the above semiconductor device.
To accomplish the above object, there is provided a semiconductor device including a plurality of memory cells, each cell having a transistor formed on a first semiconductor substrate and comprising first and second impurity regions and a gate electrode, and a capacitor comprising a first electrode connected with the first impurity region of the transistor and a second electrode formed on the first electrode with a dielectric film disposed therebetween, wherein a channel region formed between the first impurity region and the second impurity region of the transistor is vertically located on the capacitor, and a contact hole connecting the second impurity region of the transistor with the bit-line is vertically located on the channel region.
The first electrode of the capacitor is vertically connected with the first impurity region of the transistor. The first electrode, the channel region, and the first and second impurity regions of the transistor are vertically formed on the same semiconductor substrate.
The second electrode of the capacitor is formed as a structure merged with the substrate. The channel region of the transistor is vertically located on the capacitor and is formed on the back side of the first semiconductor substrate.
According to a preferred embodiment of the present invention, the capacitor may be formed as a trench capacitor which is formed by using at least one trench, or may be formed as a cylindrical-type stacked capacitor. Also, the gate electrode of the transistor may be formed as a ring structure surrounding a pillar formed on the back side of the first semiconductor substrate.
To accomplish the second object of the invention, there is provided a method for manufacturing a semiconductor device. The method comprises the steps of: forming a trench isolation region for defining an active region on a first semiconductor substrate; forming a capacitor comprising a first electrode, a dielectric film and a second electrode on the active region of the first semiconductor substrate; etching the back side of the first semiconductor substrate on which the capacitor is formed; selectively etching the back side of the first semiconductor substrate to form a plurality of pillars; and forming a gate electrode of a transistor surrounding the pillars.
A preferred embodiment of the second object of the present invention further comprises a step of attaching a second semiconductor substrate on the second electrode of the capacitor with an insulating layer disposed therebetween, before the step of etching-the back side of the first semiconductor substrate.
A bit-line contact hole for connecting a bit-line to the transistor is simultaneously formed with the gate electrode formation.
According to the present invention, since the capacitor, the channel region of the transistor, and the bit-line contact hole are located vertically with respect to one another, the cell area required for giga-bit memory devices and beyond can be achieved, and the capacitor area can be increased.
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patent: 4252579 (1981-02-01), Ho et al.
patent: 4833516 (1989-05-01), Hwang et al.
patent: 5027172 (1991-06-01), Jeon
patent: 5055898 (1991-10-01), Beilstein et al.
patent: 5177576 (1993-01-01), Kimura et al.
patent: 5316962 (1994-05-01), Matsuo et al.
patent: 5319235 (1994-06-01), Kihara et al.
patent: 5350941 (1994-09-01), Madan
patent: 5498584 (1996-03-01), Geissler et al.
Nitayama et al., “A Surrounding Isolation Merged Plate Electrode Cell with Checkered lyaout for 256 DRAMs and beyong”, 1991 IEEE, pp. 469-472, d
Bowers Charles
Huynh Yennhu B.
Pillsbury & Winthrop LLP
Samsung Electronics Co Ltd.
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