Method for manufacturing a semiconductor device

Details Method for manufacturing a semiconductor device Method for manufacturing a semiconductor device

1992-11-25

1995-01-03

Thomas, Tom

Fishing, trapping, and vermin destroying

437 89, 437913, H01L 21265

Patent

active

053786440

ABSTRACT:
A semiconductor device comprising an element separation insulator layer (5, 6, 29) is formed to surround an active region and insulate this active region from other active regions, and to have substantially uniform height throughout its periphery on a main surface of a semiconductor substrate (1). A semiconductor layer (14) is formed flat on an entire area of the active region surrounded by this element separation insulator layer (5, 6, 29) and essentially coplanar to it. The surface of the semiconductor layer (14) is used as an element formation region. This semiconductor device can remarkably reduce an error or difference between design size of the element pattern and actual size of the element, and also can prevent a short-circuiting between conductive wirings by debris.

REFERENCES:
patent: 4378627 (1983-04-01), Jambotkar
patent: 4824799 (1989-04-01), Komatsu
patent: 4923824 (1990-05-01), Fertig et al.
patent: 4925810 (1990-05-01), Kano et al.
patent: 4966861 (1990-10-01), Mieno et al.
patent: 4982269 (1991-01-01), Calligaro
patent: 5067000 (1991-11-01), Eimori et al.
patent: 5079183 (1992-01-01), Maeda et al.
patent: 5084419 (1992-01-01), Sakao
patent: 5086011 (1992-02-01), Shiota
Ghandhi, "VLSI Fabrication Principles", 1983, pp. 231-235.
IEEE (1987) FIG. 2-43, Silicon Processing for the VLSI Era, vol. 1, pp. 59-60.
Yamada et al., "Spread Source/Drain (SSD) MOSFET Using Selective Silicon Growth for 64Mbit DRAMs", IEEE Journal (1989), pp. 2.4.1-2.4.4.
Kurten et al., "Selective Low-Pressure Silicon Epitaxy for MOS and Bipolar Transistor Application", IEEE Transactions on Electron Devices, vol. ED-30, No. 11 (Nov. 1983), pp. 1511-1515.
Sagao et al., "Application of Selective Silicon Epitaxial Growth for CMOS Technology", IEDN Tech. Dig. (1984), pp. 593-596.
Endo et al., "Scaled CMOS Technology Using SEG Isolation and Buried Well Process", IEEE Transactions on Electron Devices, vol. ED-33, No. 11 (Nov. 1986), pp. 1659-1666.
Fuse et al., "A New Isolation Method with Boron-Implanted Sidewalls for Controlling Narrow-Width Effect", IEEE Transactions on Electron Devices, vol. ED-34, No. 2 (Feb. 1987), pp. 356-359.
VLSI Technology, McGraw-Hill-Verlag, 1988, pp. 79-82; Pimbley et al., "Advanced CMOS Process Technology", VLSI Electronics Microstructure Science, vol. 19.

Affiliated with

Also associated with

Rating

Method for manufacturing a semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for manufacturing a semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing a semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2211172