Method for manufacturing a semiconductor device

Details Method for manufacturing a semiconductor device Method for manufacturing a semiconductor device

1987-02-26

1988-01-19

Powell, William A.

Fishing, trapping, and vermin destroying

437 43, 437193, 156646, 156651, 156653, 156657, 1566591, 156662, H01L 21306, B44C 122, C03C 1500, C03C 2506

Patent

active

047203234

ABSTRACT:
A semiconductor device such as a MOS transistor includes floating and control gates. Between the gates is provided a composite insulating layer including a silicon nitride layer. The end portions of the composite insulating layer extend in the channel-length direction of the MOS transistor beyond the end portions of at least one of the floating and control gates.

REFERENCES:
patent: 4514897 (1985-05-01), Chiu et al.
patent: 4517732 (1985-05-01), Oshikawa
M. Kikuchi et al., A New Technique to Minimize the EPROM Cell, 1978 IEEE Int'l Electron Devices Mtg., Technical Digest, pp. 181-184.

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