Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2009-05-14
2011-10-18
Norris, Jeremy (Department: 2835)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S261000
Reexamination Certificate
active
08039755
ABSTRACT:
A circuit board element and production thereof are disclosed, whereby a noble metal is applied to a structured conductor layer on a circuit board substrate, comprising said conductor layer. The conductor layer is roughened on the surface, preferably after the structuring thereof and the noble metal applied as a layer, essentially on all of the structured roughened conductor layer, whereupon the noble metal layer surface is given a corresponding roughness.
REFERENCES:
patent: 4870746 (1989-10-01), Klaser
patent: 5827604 (1998-10-01), Uno et al.
patent: 6242079 (2001-06-01), Mikado et al.
patent: 6376052 (2002-04-01), Asai et al.
patent: 6500350 (2002-12-01), Hunt et al.
patent: 6645297 (2003-11-01), Suzuki et al.
patent: 2001/0023535 (2001-09-01), Dunn
patent: 2003/0132025 (2003-07-01), Wakihara et al.
patent: 2003/0150101 (2003-08-01), Park et al.
patent: 2003/0157264 (2003-08-01), Hutchinson et al.
patent: 2004/0239474 (2004-12-01), Dunn et al.
patent: 1 102 523 (2001-05-01), None
patent: 1 327 995 (2003-07-01), None
patent: 63262476 (1988-10-01), None
patent: 64-42896 (1989-02-01), None
patent: 02174188 (1990-07-01), None
patent: 04078471 (1992-03-01), None
patent: 06260741 (1994-09-01), None
patent: 11121926 (1999-04-01), None
patent: 2000-082871 (2000-03-01), None
patent: 2000-315854 (2000-11-01), None
patent: 2001-015927 (2001-01-01), None
Patent Abstracts of Japan of JP 11121926 dated Apr. 30, 1999.
Patent Abstracts of Japan of JP 63262476 dated Oct. 28, 1988.
Patent Abstracts of Japan of JP 02174188 dated Jul. 5, 1990.
Patent Abstracts of Japan of JP 04078471 dated Mar. 12, 1992.
Patent Abstracts of Japan of JP 06260741 dated Sep. 16, 1994.
Office Action from the Japanese Patent Office in connection with the counterpart Japanese Application No. with partial English translation.
Bauer Wolfgang
Stahr Johannes
AT & S Austria Technologie & Systemtechnik Aktiengesel
Ladas & Parry LLP
Norris Jeremy
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