Fishing – trapping – and vermin destroying
Patent
1986-03-10
1989-01-17
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437148, 437150, 437154, 437 41, 437913, 357 234, H01L 21265, H01L 2122
Patent
active
047988100
ABSTRACT:
A process for manufacturing a DMOS transistor in accordance with the present invention includes the steps of forming a layer of gate insulation (12, 14) on an N type substrate (10). A layer of polycrystalline silicon (16) is formed on the gate insulation layer. A first mask (18) is used to define the polycrystalline silicon gate (16e, 16f). A layer of silicon dioxide (20) is then formed on the gate. A second mask (22) defines the gate contact region (window 22a)) as well as where a deep body region (24) is to be formed (window 14a)). Portions of the gate insulation layer not covered by the gate are subsequently removed. The P type body region (26) and N+ source region (28) are then formed having a lateral extent defined by the edge of the gate. A conductive layer 30 is patterned, thereby leaving a gate contact and a source and body contact. A passivation layer 34 is then patterned, thereby defining bonding pads. Of importance, the above-described process uses only 4 photolithographic masking steps. In one embodiment, the transistor is laterally surrounded by an equipotential ring (EQR) which includes a field limiting ring (16g), a p region (26a), and an N+ region (28a) (formed concurrently with gates (16e, 16f), body region (26), source region 28), respectively).
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Blanchard Richard A.
Cogan Adrian
Hearn Brian E.
Leeds Kenneth E.
MacPherson Alan H.
Quach T. N.
Siliconix incorporated
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