Method for manufacturing a power chip resistor

Metal working – Method of mechanical manufacture – Electrical device making

Reexamination Certificate

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Details

C029S611000, C029S619000, C029S620000, C029S621000, C174S260000, C338S308000, C338S309000, C338S332000, C430S313000, C430S315000, C430S324000, C438S462000, C438S977000

Reexamination Certificate

active

06859999

ABSTRACT:
The invention provides for a method of manufacturing a stacked power chip resistor. The method includes adhering a first chip resistor to a second chip resistor with a glass encapsulant, connecting a first terminal of the first chip resistor to a first terminal of the second chip resistor with the first metal barrier, and connecting a second terminal on the first chip resistor to a second terminal of the second chip resistor with a second metal barrier.

REFERENCES:
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patent: 5562973 (1996-10-01), Nagasaka et al.
patent: 6124769 (2000-09-01), Igarashi et al.
patent: 6194990 (2001-02-01), Lee et al.
patent: 6311390 (2001-11-01), Abe et al.
patent: 6314637 (2001-11-01), Kimura et al.
patent: 40 30 479 A 1 (1992-04-01), None
patent: 63296201 (1988-12-01), None
patent: 06-283301 (1994-10-01), None
patent: 11016703 (1999-01-01), None
patent: WO 9838652 (1998-03-01), None
patent: WO 9953505 (1999-10-01), None

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