Method for manufacturing a multi-level interconnect structure

Details Method for manufacturing a multi-level interconnect structure Method for manufacturing a multi-level interconnect structure

2003-05-22

2004-03-30

Quach, T. N. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257S758000, C438S619000, C438S622000, C438S758000

Reexamination Certificate

active

06713835

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to the manufacture of integrated circuit chips and, more particularly, to a process for manufacturing multilevel interconnect structures for integrated circuit chips.
BACKGROUND OF THE INVENTION
Scaling down of active device dimensions in the manufacture of integrated circuits (IC) chips has improved circuit performance and increased complexity and the capability of the active devices packed on a semiconductor substrate. The full benefit of advances in active-device density may be realized only if the active devices are effectively interconnected. As the active device density increases and feature sizes shrink, the circuit performance and functional capability of an IC chip is eventually limited by the signal-transmission effectiveness and efficiency of the interconnect structure.
Multi-level interconnect structures have been developed that match the advances in active-device density by more effectively routing metallization lines between the active devices. In certain IC designs, five or more individual levels of metallization lines may be required to accommodate the active-device density. Multilevel interconnect structures arrange the metallization lines in multiple layers in which the metallization lines of each individual level are formed in an interlevel dielectric. The interlevel dielectric electrically isolates the metallization lines from one another in each level of the interconnect structure and electrically isolates metallization lines in adjacent levels.
Damascene processes are routinely used in back-end-of-line (BEOL) processing for fabricating multilevel interconnect structures. In a damascene process, trenches and vias are etched in a layer of an interlevel dielectric and filled with metal, such as copper (Cu) or a Cu-based alloy, to create metallization lines and vertical conductive paths between metallization lines in different levels. Copper has superior electromigration resistance and a lower resistivity than other candidate metals, such as aluminum, considered for in fabricating multilevel interconnect structures. Traditional subtractive etching approaches cannot be used to form copper metallization lines because copper is difficult to etch. Therefore, damascene processes are particularly meaningful for fabricating copper metallization lines.
In a dual-damascene process, the interlevel dielectric layer is conformally covered by a blanket of metal that simultaneously fills the trenches and vias. Excess overburden metal is removed from the interlayer dielectric by a process such as chemical-mechanical polishing (CMP). Metal remaining in the trenches extends substantially horizontal relative to the substrate to define metallization lines, and metal remaining in the vias provides contacts between metallization lines in adjacent levels. A single-damascene process forms trenches and vias in distinct interlevel dielectric layers and fills each with a distinct blanket deposition of metal.
As the active-device density increases and feature sizes shrink, the line-to-line spacings between adjacent, on-pitch metallization lines in individual layers and between metallization lines in adjacent layers of the multi-level interconnect structure are reduced. Shrinking the line-to-line spacings increases the line-to-line capacitance, which slows the speed of the signals carried by the metallization lines and results in propagation delay.
The line-to-line capacitance may be reduced by reducing the dielectric constant of the interlevel dielectric. To that end, one trend in multilevel interconnect structures is to form the interlevel dielectric from a dielectric material characterized by a relative permittivity or dielectric constant less than the dielectric constant of silicon oxide or fluorinated silicon glass. Generally, such low-k dielectrics are characterized by a dielectric constant less than about 4, which represents the dielectric constant of silicon oxide. Candidate low-k materials include spin-on low-k films, such as SILK commercially available from Dow Chemical Co. (Midland, Mich.), and chemical vapor deposition low-k films, such as organosilicates. The reduction in line-to-line capacitance afforded by low-k dielectrics permits adjacent metallization lines to be positioned closer together and decreases the number of levels in the multi-level interconnect structure. The effect of low-k dielectrics is to improve the performance of an IC chip for a given wiring density.
Damascene processes place stringent requirements on the properties of the material forming the interlevel dielectric layer and, hence, on the candidate low-k dielectrics projected for use as an interlevel dielectric. The host of requirements has limited the integration of low-k dielectrics into damascene processes for fabricating multilevel interconnect structures. In particular, low-k dielectrics must be compatible with the cleaning, etching, CMP and thermal treatments characteristic of a damascene process. The low-k dielectric must have sufficient mechanical strength and chemical stability to withstand all process steps.
In damascene processes, interlevel dielectric layers formed from a conventional low-k dielectric are covered by an etch stop layer as protection from photoresist stripping processes. The etch stop layer also serves as a hard mask for CMP processes that remove excess metal overburdening the interlevel dielectric after the blanket deposition that fills the vias and trenches. Conventional low-k dielectrics are soft and prone to undercutting when polished by a CMP process if the etch stop layer is omitted. Because many low-k dielectrics are hydrophilic, the etch stop layer also shields the interlevel dielectric from moisture introduced during the CMP processes and protects the interlevel dielectric from attack by aggressive post-CMP cleaning.
Although etch stop layers eliminate these adverse effects, their presence adds to the complexity of the damascene process. In particular, a distinct deposition is required to create each etch stop layer. Another disadvantage is that the most commonly used etch stop material, silicon nitride, has a rather high dielectric constant ranging between about 6 and about 8. Therefore, the presence of etch stop layers increases the effective dielectric constant and capacitance of the interlevel dielectric.
An extremely low-k dielectric for forming a multilevel interconnect structure is air, which has a dielectric constant of about unity. Mechanical strength is lent during processing by incorporating a sacrificial or removable material as a temporary interlevel dielectric and removing the sacrificial material after the levels of the multilevel interconnect structure are completed. The spaces formerly occupied by the sacrificial material are air-filled voids.
One conventional approach for forming an air dielectric uses amorphous carbon as a sacrificial material. The amorphous carbon is removed by providing passageways extending through the interconnect structure and heating in an oxidizing environment to convert the amorphous carbon to a carbonaceous gas that escapes through the passageways. However, two capping layers of silicon nitride are applied over the metallization lines of each interconnect level before the amorphous carbon is removed. Each capping layer requires a discrete lithographic patterning and etching step that adds fabrication costs and that may increase the IC chip size to account for overlay tolerances between the two capping layers. The removal of the amorphous carbon is recognized to deteriorate the material forming the metallization lines, which necessitates fully encapsulating the metallization lines with an adhesion promotion barrier layer. In addition, the sacrificial amorphous carbon is removed from each level of the interconnect structure before successive levels are formed, which adds significant complexity to the manufacture of multi-level interconnect structures.
Another conventional approach for forming an air dielectric uses a flowable oxide or hydrogen silicate glass as a sacrificial ma

Affiliated with

Also associated with

Rating

Method for manufacturing a multi-level interconnect structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for manufacturing a multi-level interconnect structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing a multi-level interconnect structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3231279