Method for manufacturing a multi-layer printed circuit board

Metal working – Method of mechanical manufacture – Electrical device making

Reexamination Certificate

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Details

C029S846000, C029S830000, C029S831000, C427S097100, C427S099300

Reexamination Certificate

active

06839964

ABSTRACT:
A method of manufacturing a multilayer printed circuit board (PCB) is provided, the PCB having blind vias connecting to power layers. A portion of the blind vias in the power layers are grouped together to form a cluster of blind vias. Signal layers, provided separate from the power layers, include signal routing channels, with at least some of the signal routing channels aligned above or below the cluster of blind vias of the power layers.

REFERENCES:
patent: 4513355 (1985-04-01), Schroeder et al.
patent: 4668332 (1987-05-01), Ohnuki et al.
patent: 4799128 (1989-01-01), Chen
patent: 4837622 (1989-06-01), Whann et al.
patent: 4864722 (1989-09-01), Lazzarini et al.
patent: 4868350 (1989-09-01), Hoffarth et al.
patent: 4916260 (1990-04-01), Broaddus et al.
patent: 5045975 (1991-09-01), Cray et al.
patent: 5148103 (1992-09-01), Pasiecznik, Jr.
patent: 5185502 (1993-02-01), Shepherd et al.
patent: 5191174 (1993-03-01), Chang et al.
patent: 5218761 (1993-06-01), Maniwa et al.
patent: 5225777 (1993-07-01), Bross et al.
patent: 5309324 (1994-05-01), Herandez et al.
patent: 5322593 (1994-06-01), Hasegawa et al.
patent: 5363280 (1994-11-01), Chobot et al.
patent: 5371654 (1994-12-01), Beaman et al.
patent: 5464950 (1995-11-01), Horiuchi et al.
patent: 5476211 (1995-12-01), Khandros
patent: 5488542 (1996-01-01), Ito
patent: 5491426 (1996-02-01), Small
patent: 5509200 (1996-04-01), Frankeny et al.
patent: 5521518 (1996-05-01), Higgins
patent: 5534784 (1996-07-01), Lum et al.
patent: 5543586 (1996-08-01), Crane, Jr. et al.
patent: 5554940 (1996-09-01), Hubacher
patent: 5557502 (1996-09-01), Banerjee et al.
patent: 5623160 (1997-04-01), Liberkowski
patent: 5701085 (1997-12-01), Malladi et al.
patent: 5786701 (1998-07-01), Pedder
patent: 5806181 (1998-09-01), Khandros et al.
patent: 5822856 (1998-10-01), Bhatt et al.
patent: 5912809 (1999-06-01), Steigerwald et al.
patent: 5917707 (1999-06-01), Khandros et al.
patent: 6050829 (2000-04-01), Eldridge et al.
patent: 6121554 (2000-09-01), Kamikawa
patent: 6378201 (2002-04-01), Tsukada et al.
patent: 6653574 (2003-11-01), Tsai et al.
patent: 632281 (1995-01-01), None
patent: 63243768 (1988-10-01), None
patent: 5-335713 (1993-12-01), None
patent: 6249924 (1994-09-01), None

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