Fishing – trapping – and vermin destroying
Patent
1985-07-02
1989-03-07
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
437 43, 437 44, H01L 21425, H01L 2978
Patent
active
048106666
ABSTRACT:
A method for manufacturing a MOSIC includes a step of forming a protective film of silicon nitride, which covers the top and side walls of a gate electrode structure including a doped polysilicon, a step of forming an interlayer insulating film and a step of forming a contact pattern in the interlayer insulating film immediately adjacent to a portion of the protective film in a self-aligned fashion with respect to the gate electrode structure. The presence of the protective film which covers the top and side walls of the doped polysilicon, which defines a gate electrode of a MOSFET, allows forming a pair of associated contact holes for drain and source regions in a self-aligned fashion, which contributes for higher integration.
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Gargini et al., "WOS: Low-Resistance Self-Aligned Source, Drain and Gate Transistors", Technical Digest of IEDM, pp. 54-57, (1981).
Chaudhuri Olik
Ricoh & Company, Ltd.
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