Method for manufacturing a monolithically integrable circuit wit

Details Method for manufacturing a monolithically integrable circuit wit Method for manufacturing a monolithically integrable circuit wit

1983-07-28

1985-04-16

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Electrical device making

29591, 204192D, 357 71, 427 38, 427 93, 427 94, 427 95, H01L 2190, H01L 2194

Patent

active

045106789

ABSTRACT:
A method of manufacturing a monolithically integrable circuit, which includes depositing an SiO.sub.2 layer on the surface of a semiconductor substrate containing p-n junctions of the circuit, at least partially covering the SiO.sub.2 layer with a first metallization supported by the SiO.sub.2 layer and containing conductor runs and electrodes capacitively coupled to the surface of the semiconductor substrate through the SiO.sub.2 layer, directly covering the first metallization with a sputtered-on SiO.sub.2 insulating layer after the first metallization is completed, covering the sputtered-on SiO.sub.2 layer with a further inorganic insulating layer generated by the plasma method, structuring the further inorganic insulating layer and the sputtered-on SiO.sub.2 layer, forming cutouts in the further inorganic insulating layer and the sputtered-on SiO.sub.2 layer above intended contact locations of the first metallization, applying a second metallization to the surface of the further inorganic insulating layer after completing the first metallization, the sputtered-on SiO.sub.2 layer and the further inorganic insulating layer, bringing the second metallization into electrical contact with the contact locations of the first metallization through the cutouts, and forming the second metallization into conductor runs.

REFERENCES:
patent: 4381595 (1983-05-01), Denda et al.
patent: 4419385 (1983-12-01), Deters
Homma, Y., "Polyimide Liftoff Technology for High Density LSI Metallization" in IEEE Trans. on Electron Devices, vol-Ed 28, No. 5, May 81, pp. 552-556.

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