Method for manufacturing a MISFET device where the conductive fi

Details Method for manufacturing a MISFET device where the conductive fi Method for manufacturing a MISFET device where the conductive fi

1997-08-13

1999-08-31

Monin, Jr., Donald L.

Semiconductor device manufacturing: process

Making device or circuit emissive of nonelectrical signal

Mesa formation

438187, 438228, H01L 21283, H01L 21336

Patent

active

059465484

ABSTRACT:
A method of manufacturing a semiconductor integrated circuit device includes the steps of forming a first conductive film on a gate oxide film in a MISFET forming region for a memory cell on a main surface of a semiconductor substrate, and forming a second conductive film via the gate oxide film to a thickness which is larger than the difference in a step between the first conductive film and the gate oxide film in a MISFET forming region for the peripheral circuit on the main surface of the semiconductor substrate, simultaneously with the formation of the second conductive film on the first conductive film in the MISFET forming region for the memory cell. Thereafter, the second conductive film is flattened by a CMP method so that the difference in the step between the second conductive film on the first conductive film in the MISFET forming region for memory cell and the gate oxide film and the difference in the step between the second conductive film in the MISFET forming region for peripheral circuit and the gate oxide film are leveled with respect to each other.

REFERENCES:
patent: 4528744 (1985-07-01), Shibata
patent: 5445998 (1995-08-01), Zimmer
patent: 5547900 (1996-08-01), Lin
patent: 5550071 (1996-08-01), Ryou
A Novel Dual String Nor (DuSnor) Memory Cell EEPROM 1.28 M.sup.2 Contactless Memory Cell Techonology for a 3V only 64 Mbit) IEDM92. 9911-993. (Electronic Materials) vol. 35, No. 5, pp. 28-32, Published by Kogyou Chousa-Kai, May, 1996.

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