Semiconductor device manufacturing: process – Making device array and selectively interconnecting
Reexamination Certificate
2003-10-31
2008-03-11
Menz, Douglas M. (Department: 2891)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
C438S129000, C257S211000
Reexamination Certificate
active
07341891
ABSTRACT:
A method for making a memory cell for reducing the cost and complexity of modifying a revision identifier (ID) or default register values associated with an integrated circuit (IC) chip, and a method for manufacturing the same. The cell, which may be termed a “Meta-Memory Cell” (MMCEL), is implemented on metal layers only and utilizes a dual parallel metal ladder structure which traverses and covers each metal and via layer from the bottom to the top of the metal layer structure of the chip. One of the metal ladders is connected to a power supply at the bottom metal layer, corresponding to a logic 1, and another metal ladder is connected to ground at the bottom metal layer, corresponding to a logic 0. The output of the MMCEL can thus be inverted at any metal or via layer and can be inverted as often as required. Significant cost savings are achieved because a revision ID or default register bits may be modified by altering only those metal layers where design changes are necessary.
REFERENCES:
patent: 5068603 (1991-11-01), Mahoney
patent: 5408428 (1995-04-01), Burgess et al.
patent: 5459355 (1995-10-01), Kreifels
patent: 5590069 (1996-12-01), Levin
patent: 5644144 (1997-07-01), Ray
patent: 5831280 (1998-11-01), Ray
patent: 6292024 (2001-09-01), Jensen et al.
patent: 6331790 (2001-12-01), Or-Bach et al.
patent: 6765245 (2004-07-01), Bansal
patent: 6933547 (2005-08-01), Catalasan et al.
patent: 7078936 (2006-07-01), Catalasan et al.
patent: 2004/0251470 (2004-12-01), Catalasan et al.
patent: 2004/0251472 (2004-12-01), Catalasan et al.
patent: 2004/0251501 (2004-12-01), Catalasan et al.
patent: 2007/0131966 (2007-06-01), Catalasan et al.
patent: 1 100 125 (2001-05-01), None
patent: 1 494 283 (2005-01-01), None
patent: 2 338 593 (1999-12-01), None
patent: WO 02/18960 (2002-03-01), None
Catalasan et al., U.S. Appl. No. 10/697,079, filed Oct. 31, 2003, entitled “Memory Cell For Modification Of Revision Identifier In An Integrated Circuit Chip,” 54 pages.
Catalasan et al., U.S. Appl. No. 10/697,286, filed Oct. 31, 2003, entitled “Memory Cell For Modification Of Default Register Values In An Integrated Circuit Chip,” 59 pages.
Catalasan et al., U.S. Appl. No. 10/697,289, filed Oct. 31, 2003, entitled “Coupling Of Signals Between Adjacent Functional Blocks In An Integrated Circuit Chip,” 77 pages.
Office Action, mailed Aug. 10, 2006, in U.S. Appl. No. 10/697,079, filed Oct. 31, 2003, 6 pages.
Office Action, mailed Apr. 19, 2005, in U.S. Appl. No. 10/697,289, filed Oct. 31, 2003, 7 pages.
Office Action, mailed Sep. 2, 2005, in U.S. Appl. No. 10/697,289, filed Oct. 31, 2003, 9 pages.
European Search Report, mailed Sep. 14, 2005, from European Patent Appln. No. 04016857.7, 3 pages.
European Search Report for European Appln. 04013796.0-2203 mailed Nov. 16, 2004.
Office Action, mailed Feb. 21, 2006, in U.S. Appl. No. 10/697,079, filed Oct. 31, 2003, 8 pages.
European Search Report for European Appln. 04013796.0-2203 mailed Oct. 26, 2004.
Catalasan Manolito M
Rakshani Vafa J
Sippel Tim
Spittles Edmund H
Unda Richard
Broadcom Corporation
Menz Douglas M.
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