Method for manufacturing a massive parallel interconnection atta

Details Method for manufacturing a massive parallel interconnection atta Method for manufacturing a massive parallel interconnection atta

1996-08-13

1999-04-13

Graybill, David

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Insulative housing or support

438611, 438612, 438623, 428620, H01L 2148

Patent

active

058937277

ABSTRACT:
A method of fabricating an electrical interconnect are provided. A first transparent dielectric layer is disposed on top of a support structure. A conductive circuit layer is plated above the first dielectric layer. Separate conductive layers are plated on top of the conductive circuit layer to produce conductive vias. A second transparent dielectric layer is disposed around the conductive layers. Contact tips are electrically connected to the top surface of the separate conductive layers. The interconnect may be visually aligned so that the contact tips brought into contact with target connections. In addition, the support structure may be partially removed to allow a flexible interconnect.

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