Liquid crystal cells – elements and systems – Nominal manufacturing methods or post manufacturing...
Reexamination Certificate
1999-11-29
2001-02-13
Sikes, William L. (Department: 2871)
Liquid crystal cells, elements and systems
Nominal manufacturing methods or post manufacturing...
C349S192000, C216S023000, C216S058000, C216S072000, C216S059000, C438S030000, C438S158000, C438S689000
Reexamination Certificate
active
06188461
ABSTRACT:
This application claims the benefit of Korean Application No. P97-54962, filed in Korea on Oct. 24, 1997, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention The present invention relates to a method for manufacturing a liquid crystal display (or “LCD”) device including a thin film transistor (or “TFT”). More particularly, the present invention relates to a method for etching a panel of an LCD in which the end point of the etching period is exactly detected so that an etched layer is not over-etched.
2. Discussion of Related Art
Referring to
FIG. 1
, showing a conventional LCD arrangement, and
FIG. 2
, showing the cross sectional view along with the reference line II—II in
FIG. 1
, the conventional LCD comprises a plurality of gate lines
70
on a substrate
10
and a plurality of data lines
80
. The gate lines
70
and the data lines
80
intersect each other in a substantially perpendicular arrangement to form an LCD matrix. The LCD further comprises a pixel electrode
40
at each area in the matrix surrounded by two neighboring gate lines
70
and two neighboring data lines
80
. A TFT
31
is provided connected to the pixel electrode
40
at the intersection portion of one gate line
70
and one data line
80
. An overlapped portion of the pixel electrode
40
and the gate line
70
is a storage capacitance electrode
35
.
The TFT
31
comprises a gate electrode
70
a
extruded from the gate line
70
, a source electrode
80
a
extruded from the data line
80
, and a drain electrode
80
b
which faces the source electrode
80
a
. The TFT
31
further comprises a semiconductor layer
90
over the gate electrode
70
a
on a gate insulation layer
50
covering the gate line
70
and the gate electrode
70
a
. The semiconductor layer
90
is in contact with the source electrode
80
a
and the drain electrode
80
b
. In order to ohmically contact the source
80
a
and the drain
80
b
electrodes with the semiconductor layer
90
, doped semiconductor layers
92
a
and
92
b
are formed under the source electrode
80
a
and the drain electrode
80
b
, respectively.
The LCD also includes a protection layer
55
covering the whole surface of the substrate
10
, which includes a TFT
31
, a contact hole
37
which exposes a portion of the drain electrode
80
b
by etching the protection layer
55
, and the pixel electrode
40
coupled to the drain electrode
80
b
through the contact hole
37
. If the duration of the etching process on the protection layer
55
when the contact hole
37
is formed lasts longer than a desired interval, then the resulting contact hole is larger than the initially desired size. As a result, the pixel electrode
40
does not cover the contact hole
37
entirely and leaves exposed a portion of the drain electrode
80
b
. This situation allows the exposed portion of the drain electrode
80
b
to be in contact with moisture and oxygen in the atmosphere. As a result, the drain electrode
80
b
can be corroded and short circuited, as shown in FIG.
2
.
In order to understand why the contact hole is over-etched, we will explain the processing for manufacturing the LCD in detail with reference to
FIGS. 3A and 3B
.
As seen in
FIG. 3A
, a gate electrode
70
a
including aluminum or an aluminum alloy is formed on a transparent substrate
10
. A gate insulating layer
50
including a silicon nitride (SiN
x
) or a silicon oxide (SiO
x
) is deposited on the substrate
10
covering the gate electrode
70
a
. A semiconductor layer
90
is formed on the gate insulation layer
50
over the gate electrode
70
a
. Two doped semiconductor layers
92
a
and
92
b
are formed on the two sides of the semiconductor layer
90
. A data line
80
including a chromium material is formed on the gate insulation layer
50
. A source electrode
80
a
extruding from the data line
80
is formed on the doped semiconductor layer
92
a
. A drain electrode
80
b
facing the source electrode
80
a
is formed on the doped semiconductor layer
92
b
. After the TFT including the source
80
a
and drain
80
b
electrode is formed, a protection layer
55
including an Si bonding structure such as a silicon nitride, a silicon oxide, or a benzocyclobutene (or “BCB”) is formed on the substrate including the TFT. A photoresist is coated on the protection layer
55
using a spin coating method. The photoresist is exposed and developed using a mask to form a pattern layer
60
in which a portion having a scale d1 is removed from the photo resist.
After the panel of the LCD, as seen in
FIG. 3A
, is placed in an etching chamber, the exposed portion of the protection layer
55
is removed using SF
6
gas as an etchant. When the etchant is in contact with the surface of the protection layer
55
, the SF
6
gas reacts with the Si radical of the protection later
55
, so that the exposed portion of the protection layer
55
is removed from the surface while producing a volatile material such as an SiF
4
gas. After the exposed portion of the protection layer
55
is entirely removed, the surface of the drain electrode
80
b
is revealed. At that time, the amount of SiF
4
gas produced is decreased conspicuously. In other words, when the SiF
4
gas is being produced, the etching process is proceeding. The conspicuous reduction in the production of SiF
4
gas is an indication that the etching process is ended. We can determine the time that the optimum etching duration end point is reached by monitoring the amount of the SiF
4
gas produced.
However, despite the hundreds of thousands of the contact holes
37
present in the arrangement, the total area of the exposed portion of the protection layer is less than 1% of the total area of the panel, because the plane view area of the contact hole is less than tens of &mgr;m
2
. Therefore, it is difficult to detect the etching duration end point exactly using the small amount of the SiF
4
gas reproduced from this tiny area. For example, in this method for detecting the SiF
4
gas, an electrical device, referred to as an etching end point detector, in which the amount of the SiF
4
gas produced is converted to electrical voltage according to the time duration is used. As seen in
FIG. 4
, the difference between the indicated voltage (1) during the time that the etching process is proceeding and the indicated voltage (3) during the time that the etching process is finished is difficult to distinguish because of the relatively slight difference between the two voltage levels. This results in difficultly in determining the exact duration of the etching period and the proper end point for the etching. By not determining the exact desired end time of the etching process, generally, the etching process continues after the desired end time is passed, resulting in the protection layer
55
being over-etched so that the contact hole has a d2 scale instead of the desired d1 scale as shown in FIG.
3
B.
At this time, the pattern layer
60
is removed and an indium tin oxide (or “ITO”) layer is deposited on the protection layer
55
. The ITO layer is patterned to form a pixel electrode
40
. In this case, the drain electrode
80
b
is not entirely covered by the pixel electrode
40
. The drain electrode
80
b
is exposed through the contact hole
37
enlarged by the over-etch, as seen in FIG.
2
. The exposed portion of the drain electrode
80
b
contacts with moisture and the oxygen in the atmosphere. As a result, the drain electrode
80
b
can corrode and finally it can be opened to form a short circuit.
The foregoing discussion describes the over-etch problem of the contact hole formed at the protection layer. A similar problem may result when a metal layer is etched to form a gate or data line, or when a semiconductor layer is formed.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method for manufacturing a device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method for detec
L.G. Philips LCD Co., Ltd.
Morgan & Lewis & Bockius, LLP
Sikes William L.
Vu Quynh-Nhu
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