Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Including integrally formed optical element
Reexamination Certificate
1998-11-02
2002-10-01
Chaudhuri, Olik (Department: 2813)
Semiconductor device manufacturing: process
Making device or circuit emissive of nonelectrical signal
Including integrally formed optical element
C438S714000, C438S723000, C438S724000
Reexamination Certificate
active
06458613
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a manufacturing method for a liquid crystal display device using a selective etching method. More specifically, the present invention relates to an etching method for manufacturing a liquid crystal display having a TFT (thin film transistor), gate bus lines, data bus lines which include a refractory metal such as Mo, Ta, Ti, MoSi, TaSi or TiSi, and a passivation layer covering them, wherein the refractory metal is not damaged by the etchant used for forming the passivation layer.
2. Description of the Background Art
Generally, a thin film type liquid crystal display device includes a lower plate, an upper plate joined to the lower plate, and a liquid crystal disposed therebetween. At the outer portions of the two connected plates, polarizing plates are attached. That is, the upper plate includes an inner side having a color filter and a common electrode, and an outer side having a polarizing plate. The lower plate includes an outer side having a polarizing plate as well, and an inner side having a plurality of gate bus lines
20
and data bus lines
10
arranged perpendicular to and crossing with each other, and a pixel electrode
55
positioned at an inner space defined by the crossed gate bus lines
20
and the data bus lines
10
, as shown in FIG.
1
. That is, a plurality of the gate bus lines
20
are arranged to extend in a horizontal direction on the lower plate, and gate electrodes
21
are extended from the gate bus lines
20
. A plurality of the data bus lines
10
are arranged to extend perpendicularly to the gate bus lines
20
and source electrodes
11
are extended from the data bus lines
10
. Drain electrodes
31
facing the source electrodes
11
are disposed so that the TFT switching elements, including the gate electrodes
21
, the source electrodes
11
and the drain electrodes
31
, are completed.
To drive the LCD, each data bus line
10
is connected to an output of a signal driver IC generating the data signal of the picture, and each gate bus line
20
is connected to a output of a scan driver IC generating the scan signal of the picture.
A process to manufacture the lower plate of the LCD is explained below referring to
FIGS. 1
to
4
c
.
FIG. 1
is a plane view showing the lower plate of a conventional liquid crystal display device.
FIGS. 2
a
-
2
c
,
3
a
-
3
c
, and
4
a
-
4
c
are cross-sectional views showing a conventional method for etching the passivation layer covering a switching element as denoted by line a—a in
FIG. 1
, a gate pad
22
as denoted by line b—b, and data pad
12
as denoted by line c—c, respectively.
As shown in the figures, the lower plate
1
is formed using a transparent insulating substrate such as glass. On the lower plate
1
, a metal layer including molybdenum (Mo) is deposited by sputtering. A plurality of gate bus lines
20
extending in the horizontal direction and a plurality of gate electrodes
21
extending from the gate bus lines
20
are formed by patterning the molybdenum metal layer on the lower plate
1
. A gate pad
22
is formed at a start end of each gate bus line
20
for connection to the output of the scan driver IC generating the scan signal of the picture.
As shown in
FIGS. 2
a
-
2
c
, the lower plate includes a gate insulation layer
23
, such as SiN
x
, or SiO
x
disposed thereon. Such layer has a good adhesive property with an amorphous silicon and high insulating property.
On the gate insulation layer
23
, an amorphous silicon (a-Si) or CdSe is deposited and patterned to form a semiconductor layer
13
. On the semiconductor layer
13
, an ohmic contact layer
14
is formed for providing a good ohmic contact between the semiconductor layer
13
and the source electrode
11
and the drain electrode
31
.
On the entire surface of the lower plate
1
after the above mentioned processes have been completed, a metal layer including molybdenum, is deposited by sputtering and patterned to form a plurality of data bus lines
10
extending in the vertical direction as shown in FIG.
1
. Near the intersections of the gate bus lines
20
and the data bus lines
10
, the source electrode
11
extends from the data bus line
10
and contacts one side of the ohmic contact layer
14
, and the drain electrode
31
faces the source electrode
11
and contacts the other side of the ohmic contact layer
14
. The data pad
12
is formed at the start end of each data bus line
10
for connection to the output of the signal driver IC generating the data signal of the picture supplied to the LCD.
After performing the above mentioned processing, a TFT switching element, which includes the gate electrode
21
, the semiconductor layer
13
, the source electrode
11
and the drain electrode
31
, is formed.
Over the switching element, a passivation layer
40
is formed by depositing and/or coating an insulating layer including a Si bonding structure such as SiN
x
, SiO
x
, or BCB (Benzocycobutene), as shown in
FIG. 2
a
. As shown in
FIGS. 2
b
,
3
b
, and
4
b
after coating a photo-resist
60
on the passivation layer
40
using a spin coating method, the photo-resist
60
is patterned by exposure using a mask. Here, the patterned photo-resist
60
covers the entire surface of the passivation layer
40
except surface portions covering the drain electrode
31
, the gate pad
22
and the data pad
12
.
As a result of etching the lower plate
1
including the patterned photo-resist
60
in the etching chamber using SF
6
+O
2
or CF
4
+O
2
as an etching gas to remove the uncovered portion of the passivation layer
40
, a contact hole
50
is formed. Through the contact hole
50
, a portion of the drain electrode
31
as shown in
FIGS. 2
b
and
2
c
is exposed. The passivation layer
40
uncovered by the photo-resist
60
over the gate pad
22
and the data pad
12
is also etched by the etching gas such as SF
6
+O
2
or CF
4
+O
2
so that the pads
12
and
22
are exposed as shown in
FIGS. 3
b
-
3
c
and
4
b
-
4
c
, respectively. All of the photo-resist
60
is removed by the etching gas, SF
6
+O
2
or CF
4
+O
2
.
An ITO (Indium Tin Oxide) layer is deposited via sputtering on the entire surface of the passivation layer
40
having the contact hole
50
. On the ITO layer, a photo-resist is coated via a spin coating method and is then patterned. By etching the lower plate
1
having the patterned photo-resist using an etching solution such as HCl, pixel electrodes and terminals contacting pads
12
and
22
are formed. After that, the remaining photo-resist on the lower plate
1
is removed using an organic solution including NMP (N-Methyl-Pyrrolidone), alcohol and amine.
Through the terminals, the gate pad
22
is connected to the output of the scan driver IC and the data pad
12
is connected to the output of the signal driver IC.
According to the conventional method for manufacturing the LCD as described above, the step of exposing the drain electrode
31
is explained below in greater detail with reference to
FIGS. 2
b
and
2
c
. The etching process for the passivation layer
40
is performed by a chemical reaction in which the F radical of the SF
6
+O
2
or CF
4
+O
2
gas reacts with the Si
4
+
of the passivation layer
40
to form a volatile gas such as a SiF
4
. Therefore, the portions of the passivation layer
40
that are not covered by the photo-resist
60
react with the SF
6
+O
2
or CF
4
+O
2
gas to form a volatile SiF
4
gas so that these portions are removed. However, a portion of the drain electrode
31
is also exposed as shown in
FIG. 2
b
. Unfortunately, the molybdenum of the drain electrode
31
easily reacts with the SF
6
+O
2
or CF
4
+O
2
gas used for etching the passivation layer
40
. Therefore, the exposed portion of the drain electrode
31
is damaged by etching when the passivation layer is etched, as shown in
FIG. 2
c.
Referring to
FIGS. 3
a
and
3
b
, the process for exposing the gate pad
22
is explained below in detail. As me
Birch & Stewart Kolasch & Birch, LLP
Chaudhuri Olik
Kielin Erik
LG Electronics Inc.
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