Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2006-05-02
2006-05-02
Chen, Kin-Chan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S106000, C438S107000, C438S745000
Reexamination Certificate
active
07037844
ABSTRACT:
A method for manufacturing a chip housing includes a first basis having a photolithograpically structurable layer on a main face, structured into a cover. A chip has the structure at a main face between first contact elements. A second photolithograpically structurable layer applied to the main face is structured forming a recess surrounded by a wall near the structure exposing the first contact elements. Then, the first basis and the chip are merged with the structure and the cover facing and aligned with each other, and the recess closed by the cover. Removing the first basis leads to an on-chip cavity. Afterwards, a second basis and the chip are merged with the first contact elements connected to the second basis via a conductive structure. Afterwards, the second basis is removed for exposing the conductive structure. The method is less subject to cost and size limitations of known housing technologies.
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Dāche Frank
Dangelmaier Jochen
Ehrler Günter
Meckes Andreas
Weber Michael
Chen Kin-Chan
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
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