Boots – shoes – and leggings
Patent
1983-03-22
1986-04-22
Chin, Gary
Boots, shoes, and leggings
364488, 357 40, G06F 1546
Patent
active
045846537
ABSTRACT:
A method for manufacturing a gate array IC device in which the turn-around time on design is short, the system design is simple, and the memory area for designing is reduced. The method includes manufacturing a master bulk pattern of a basic cell array on the semiconductor substrate, and storing, in semi-permanent memory, symbol data and detailed data for standard macro cells and standard expanded macro cells prior to designing a logic system. Each macro cell comprises one or more basic cells and has a basic logic function. Each expanded macro cell comprises plural macro cells and has a more complicated and sophisticated logic function than the macro cells. In addition, the logic functions of the expanded macro cells are standard in the logic system design technology area. When a designer creates a logic system, only symbol data for the macro cells and the expanded macro cells, and the connections thereof are used and stored in the memory, so that it is relatively easy to design the system. Actual conductive wiring patterns are synthesized from the logic system data and the detailed data; consequently these patterns are produced on the semiconductor substrate which is already provided with a master bulk pattern so as to connect the basic cells in accordance with the design.
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Chih Samuel
Ohba Osam
Chin Gary
Fujitsu Limited
Fujitsu Microelectronics Inc.
Herndon Heather R.
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