Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2009-04-21
2011-11-22
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S270000, C438S454000, C438S589000, C257SE21410, C257SE21547
Reexamination Certificate
active
08062954
ABSTRACT:
A method for manufacturing a field plate in a trench of a power transistor in a substrate of a first conductivity type is disclosed. The trench is formed in a first main surface of the substrate.
REFERENCES:
patent: 4255207 (1981-03-01), Nicolay et al.
patent: 4635090 (1987-01-01), Tamaki et al.
patent: 5082795 (1992-01-01), Temple
patent: 5283201 (1994-02-01), Tsang et al.
patent: 5973360 (1999-10-01), Tihanyi
patent: 6406975 (2002-06-01), Lim et al.
patent: 7005351 (2006-02-01), Henninger et al.
patent: 7303961 (2007-12-01), Weber et al.
patent: 102 34 996 (2008-01-01), None
Infineon - Technologies AG
Slater & Matsil L.L.P.
Thomas Toniae
Wilczewski Mary
LandOfFree
Method for manufacturing a field plate in a trench of a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for manufacturing a field plate in a trench of a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing a field plate in a trench of a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4300142