Method for manufacturing a complementary MOS type semiconductor

Details Method for manufacturing a complementary MOS type semiconductor Method for manufacturing a complementary MOS type semiconductor

1985-12-24

1988-05-10

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 34, 437192, 437203, 437982, H01L 21425, H01L 21441

Patent

active

047435640

ABSTRACT:
A method for manufacturing a CMOS type semiconductor device is shown which includes the following steps. A first and a second conductive diffusion region are formed in a well region and a semiconductor substrate, respectively, and a gate electrode is formed thereon. An insulation layer is formed on the semiconductor substrate and the well region. A contact hole is opened by selectively removing the insulation layer corresponding to the first and the second conductive diffusion regions. At least one metal layer selected from a group consisting of metal and metal silicide having a high melting point is formed on an exposed surface of the first and the second conductive diffusion regions. The semiconductor substrate is heated to melt at least part of the insulation layer and form a tapered portion. A wiring layer is formed on the contact hole. This method prevents the contact resistance from increasing, the impurity of one region from diffusing into the other impurity regions, the impurity of the impurity regions from decreasing, and improves the reliability of the wiring layer by forming a tapered contact hole. These advantages permit high component density by miniaturizing the device.

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