Method for manufacturing a capacitor of a trench DRAM cell

Details Method for manufacturing a capacitor of a trench DRAM cell Method for manufacturing a capacitor of a trench DRAM cell

1998-04-02

1999-11-16

Chaudhuri, Olik

Semiconductor device manufacturing: process

Making passive device

Trench capacitor

438386, 438243, 438246, 257301, H01L 218242

Patent

active

059857293

ABSTRACT:
A silicon oxide layer is formed on the wafer to act as a pad layer. A silicon nitride layer is then formed on the silicon oxide layer to have a thickness approximate 1500-2000 angstroms. At least one trench is then created in the wafer. Then, an ion implantation process is performed with at least one titled angle to dope ions into the surface of the trenches. A LPD-oxide is selectively deposited in the trench. Then, a polysilicon layer is formed on the LPD-oxide and on the surface of the silicon nitride layer. Next, the polysilicon layer is etched to generate polysilicon side-wall spacers. The LPD-oxide is etched using the polysilicon side-wall spacers and the silicon nitride layer as an etching mask. The polysilicon side-wall spacers are then removed. A first conductive layer is formed on the silicon nitride layer, and refilled into the first trenches. The first conductive layer is then etched to at least to expose the LPD-oxide. The LPD-oxide is removed. A dielectric layer is then conformally deposited along the surface of the first storage nodes. A second conductive layer is deposited on the dielectric layer and refilled into the trench.

REFERENCES:
patent: 4672410 (1987-06-01), Miura et al.
patent: 5793077 (1998-08-01), Tseng
B.W. Shen et al., Scalability of a Trench Capacitor Cell for 64Mbit DRAM, 1989 IEEE, pp. 27-30.
L. Nesbit et al., A 0.6.mu.m.sup.2 256Mb Trench DRAM Cell with Self-Aligned Buried Strap (BEST), 1993 IEEE, pp. 627-630.
Tetsuya Homma et al., A Selective SiO.sub.2 Film-Formation Technology Using Liquid-Phase Deposition for Fully Planarized Multilevel Interconnections, J. Electrochem. Soc., vol. 140, No. 8, Aug. 1993, pp. 2410-2414.
K.P. Muller et al., Trench Storage Node Technology for Gigabit DRAM Generations, 1996 IEEE, pp. 507-510.

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