Fishing – trapping – and vermin destroying
Patent
1992-10-05
1994-06-07
Beck, Shrive
Fishing, trapping, and vermin destroying
437 60, 437919, 437977, 148DIG1, 148DIG14, 148DIG138, H01L 21265
Patent
active
053189205
ABSTRACT:
A silicon layer having semispherical protrusions of about 100 nm is formed as a lower electrode of a capacitor by low pressure vapor deposition method. A silicon oxide film is formed by oxidizing the surface of this silicon layer. The intervals between the rough portions of the silicon layer are increased by removing this silicon oxide film. Thereafter, a dielectric layer and an upper electrode are formed. In other methods, after the formation of the silicon layer having the roughness, thermal treatment is continuously carried out in oxygen-free atmosphere to increase radius of curvature of the roughness of the silicon layer. Thereafter, the dielectric layer and the upper electrode are formed.
REFERENCES:
patent: 4977098 (1990-12-01), Yu et al.
patent: 5037773 (1991-08-01), Lee et al.
patent: 5043780 (1991-08-01), Fazan et al.
patent: 5135886 (1992-08-01), Manocha et al.
patent: 5208479 (1993-05-01), Mathews et al.
M. Yoshimaru et al., "Rugged Surface Poly-Si Electrode And Low Temperature Deposited Si.sub.3 N.sub.4 For 64MBIT And Beyond STC Dram Cell", CH2865-4/90/0000-0659, IEDM90 659-IEDM90 662, 27.4.1-27.4.4, 1990.
M. Sakao et al., "A Capacitor-Over-Bit-Line (COB) Cell With A Hemispherical-Grain Storage Node For 64Mb Drams", Microelectronics Research Laboratories, NEC Corp., CH2865-4/90/0000-0655, IEDM90 655-IEDM90 658, 27.3.1.-27.3.4, 1990.
Pierre C. Fazan et al., "Electrical Characterization Of Textured Interpoly Capacitors For Advanced Stacked Drams", Micron Technology Inc., CH2865-4/90/0000-0663, IEDM90 663-IEDM90 666, 27.5.1.-27.5.4., 1990.
"Fabrication of Storage Capacitance-Enhanced Capacitors with a Rough Electrode", by Yoshio Hayashide et al. Japanese Journal of Applied Physics, vol. 29, No. 12, Dec. 1990, pp. L2345-L2348.
"New stacked capacitor structure using hemispherical-grain polycrystalline-silicon electrodes", by H. Watanabe et al., Appl. Phys. Lett. 59 (3), Jan. 21, 1991, pp. 251-253.
Beck Shrive
Mitsubishi Denki & Kabushiki Kaisha
Utech Benjamin L.
LandOfFree
Method for manufacturing a capacitor having a rough electrode su does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for manufacturing a capacitor having a rough electrode su, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing a capacitor having a rough electrode su will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-792460