Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Forming lateral transistor structure
Reexamination Certificate
1998-12-16
2001-09-18
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Forming lateral transistor structure
C438S327000
Reexamination Certificate
active
06291303
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a bipolar junction device structure and its method of manufacture. More particularly, the present invention relates to a high-voltage compatible, bipolar junction device structure and its method of manufacture.
2. Description of Related Art
In some high-voltage circuit design, parasitic dipolar devices are often required. However, because earlier versions of the vertical bipolar junction transistor (BJT) have a large base width or lack a double diffusion drain (DDD) structure , gain of the transistor is too small. Yet, a lateral bipolar transistor has an even smaller gain, and hence its applications are even more restrictive.
FIG. 1
is a cross-sectional view showing a conventional vertical bipolar junction transistor. In
FIG. 1
, the substrate
100
is an N-doped region. The substrate
100
serves as a collector for the bipolar transistor, and the N
+
region
102
acts as a contact area for the collector. The well
104
is a P-doped region acting as a base, and the P
+
regions
106
serve as contact areas for the base. The emitter
108
is another N
+
region within the P-well
104
.
The structure shown in
FIG. 1
is a typical npn vertical bipolar junction transistor. When proper voltages are applied, electrons are emitted from the emitter
108
through the base
104
and inject into the substrate
100
, which serves as a collector. The path taken by the electrons is known as the base width and is represented by w in FIG.
1
. Since base width of a conventional vertical BJT is rather large, gain of the transistor is small. Hence, efficiency of the device is low.
FIG. 2
is a cross-sectional view showing a conventional lateral bipolar junction transistor. In
FIG. 2
, the substrate
200
is an N-doped region. The substrate
200
has a well region
202
. The well
202
is a P-doped region serving as a base. The P
+
region
204
within the well
202
serves as a contact area for the base. The emitter
206
and the collector
208
are two N
+
regions formed on each side of the P
+
base region
204
within the well
202
. The structure shown in
FIG. 2
is a typical npn lateral bipolar junction transistor.
Due to the presence of a contact area
204
between the emitter
206
and the collector
208
, the rate of movement of electrons from the emitter
206
to the collector
208
is greatly reduced. Moreover, some electrons may be absorbed within the contact area
204
. Therefore, gain of the lateral bipolar junction transistor is even less than the vertical BJT and more restrictions are imposed upon circuit applications.
In light of the foregoing, there is a need to provide an improved bipolar junction transistor structure.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a vertical bipolar junction transistor having a smaller base width such that a larger gain for the transistor is obtained.
In another aspect, the invention provides a lateral bipolar junction transistor having a higher gain that can be used in circuits requiring different voltage sources.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of forming a bipolar junction device on a substrate of the first conductive type. Three regions including a first region, a second region and a third region are patterned out of a substrate. A vertical npn bipolar junction transistor, a lateral npn bipolar junction transistor and a lateral pnp bipolar junction transistor are formed in the first region, the second region and the third region respectively.
The method includes the steps of forming a P-type first well in both the first region and the second region, and an N-type first well in the third region. Thereafter, an N-type second well is formed within the P-type first well of the first region, two mutually isolated N-type second wells are formed within the P-type first well of the second region, and two mutually isolated P-type second wells are formed within the N-type first well of the third region.
Next, isolating structures are formed in neighboring areas between the first, second, third regions and the first wells as well as the neighboring areas between the first well and the second well. Subsequently, an N-type first doped region is formed within the second well of the first region, two mutually isolated N-type first doped regions are formed in the second well of the second region, and an N-type first doped region is formed in the first well of the third region.
Thereafter, two mutually isolated P-type second doped regions are formed within the first well of the first region, a P-type second doped region is formed within the first well of the second region, and then two mutually isolated P-type second doped regions are formed within the second well of the third region.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 4120707 (1978-10-01), Beasom
patent: 4403395 (1983-09-01), Curran
patent: 4966858 (1990-10-01), Masquelier et al.
patent: 5066602 (1991-11-01), Takemoto et al.
patent: 5163178 (1992-11-01), Gomi et al.
patent: 5360750 (1994-11-01), Yang
patent: 5489541 (1996-02-01), Yang et al.
Silicon Processing for the VLSI Era vol. 3: The Submicron Mosfet, Sunset Beach, CA, 1995, pp. 557-560.*
Wolf, S., Tauber R.N.; Silicon Processing for the VLSI Era vol. 1: Process Technology, Lattice Press, Sunset Beach, CA, 1986, pp. 124, 280-283.
Lattin Christopher
Niebling John F.
United Microelectronics Corp.
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