Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2003-10-20
2009-08-25
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
Reexamination Certificate
active
07581080
ABSTRACT:
The present invention is capable of placing or loading input data into a 2D or 3D array of processing elements interconnected in a variety of ways, and moving the data around by using a combination of shifts, e.g. north, south, east, west, which can be combined in any desired manner. The exact type and combination of shifts depends upon the particular data manipulation desired. As the sifting proceeds, each processing element is presented with a plurality of different array values. Each processing element can conditionally load any of the values it sees into the output result. The timing of the loading is achieved by monitoring a local counter. In a preferred embodiment, when the value in the local counter is non-positive, the current array value is selected as the final output for the output result. In general, each local counter is initialized to a different positive value and, at certain points in the shifting process, the counter is decremented. The initial value of the counter depends upon its location, and is given by the general function f(x_Index, y_Index, z_Index), with the exact form of f( ) depending upon the particular data manipulation desired.
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Chan Eddie P
Jones Day
Lindlof John
Micro)n Technology, Inc.
Pencoske Edward L.
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