Method for making vertical MOSFET with reduced bipolar effects

Details Method for making vertical MOSFET with reduced bipolar effects Method for making vertical MOSFET with reduced bipolar effects

1984-02-22

1986-05-13

Roy, Upendra

Metal working

Method of mechanical manufacture

Assembling or joining

29571, 29577C, 148 15, 148187, 357 234, H01L 2978

Patent

active

045877130

ABSTRACT:
A vertical MOSFET device includes a semiconductor wafer having source, body and drain regions of alternate conductivity type disposed therein. The source and drain regions are located so as to define the length and width of a channel region in the body region at a surface of the wafer. The body region further includes a similar conductivity type supplementary region having a relatively high areal dopant concentration. The supplementary region, which can be fabricated by ion implantation, extends laterally beneath a portion of the channel region. A source electrode is disposed on one wafer surface and a drain electrode is disposed on an opposing wafer surface.

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"A Highly Reliable 16 Output High Voltage NMOS/CMOS Logic IC with Shielded Source Structure", H. Wakaumi et al., Proceedings of IEDM Meeting held in Washington, D.C., Dec. 1983, pp. 416-419.
"Parasitic Effect-Free, High Voltage MOS ICs with Shielded Source Structure", H. Sakuma et al., Proceedings of IEDM Meeting held in San Francisco, California, Dec. 1982, pp. 254-257.

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