Method for making vertical MOS having a deep source region near

Details Method for making vertical MOS having a deep source region near Method for making vertical MOS having a deep source region near

1994-03-17

1995-03-14

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 41, 148DIG126, H01L 21265

Patent

active

053977289

ABSTRACT:
A semiconductor device includes a first region, a well-shaped second region formed in the first region and a third region formed in the well-shaped second region, both the first region and the third region have a first conductive type, the well-shaped second region has a second conductive type. A gate electrode is formed on a channel of the well-shaped second region. The channel is sandwiched between the first region and the third region. According to the present invention, the depth of the third region is very deep in a portion near the channel and is very shallow in a portion far from the channel. A resistance of the well-shaped second region near a portion of the third region far from the channel is lower than near the portion of the third region near the channel.

REFERENCES:
patent: 4433468 (1984-02-01), Kawamata
patent: 4803532 (1989-02-01), Mihara
patent: 4978626 (1990-12-01), Poon et al.
patent: 5008720 (1991-04-01), Uenishi
patent: 5024960 (1991-06-01), Haken
patent: 5073519 (1991-12-01), Rodder
patent: 5079180 (1992-01-01), Rodder
patent: 5089435 (1992-02-01), Akiyama

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