Liquid crystal cells – elements and systems – Particular structure – Having significant detail of cell structure only
Reexamination Certificate
2000-04-26
2004-11-02
Chowdhury, Tarifur R. (Department: 2871)
Liquid crystal cells, elements and systems
Particular structure
Having significant detail of cell structure only
C349S155000, C264S129000, C427S133000
Reexamination Certificate
active
06812990
ABSTRACT:
FIELD OF THE INVENTION
The present invention describes thick film photolithographic molds, methods of making thick film photolithographic molds, and methods of using thick film photolithographic molds to form spacers on a substrate. The thick film photolithographic molds preferably comprise an epoxy bisphenol A novolac resin. The present invention also describes sol gel spacers comprising sodium silicates and potassium silicates. The thick film photolithographic molds and sol gel spacers of the present invention can be used in flat panel displays, such as field emission displays and plasma displays.
BACKGROUND OF THE INVENTION
FIG. 1
shows a cross sectional view of a portion of a prior art FED
100
. FED
100
includes a cathode, or baseplate
102
and an anode, or faceplate
104
. Baseplate
102
includes a substrate
106
, a plurality of conical field emitters
108
, an insulating layer
110
, and a conductive grid layer
112
. Insulating layer
110
is disposed over substrate
106
, and grid layer
112
is disposed over insulating layer
110
. Insulating layer
110
defines a plurality of void regions
114
, and each emitter
108
is disposed over substrate
106
in one of the void regions
114
. Grid layer
112
defines a plurality of apertures
116
. Each aperture
116
corresponds to, and overlies, one of the void regions
114
. The apertures
116
are positioned so that (1) the grid layer
112
does not obstruct a path
117
between the upper tips of the emitters
108
and the faceplate
104
and (2) a portion of the grid layer
112
is proximal to the tip of each emitter
108
. Baseplate
102
also includes a plurality of conductive row and column lines
118
disposed between emitters
108
and substrate
106
.
Faceplate
104
includes a glass plate
120
, a transparent conductor
122
, and a phosphor layer
124
. Transparent conductor
122
is disposed on one major surface of glass plate
120
, and phosphor layer
124
is disposed on transparent conductor
122
. The faceplate
104
and baseplate
102
are spaced apart from one another and are disposed so that the phosphor layer
124
is proximal to the grid layer
112
.
FED
100
also includes a plurality of spacers
130
disposed between the faceplate
104
and baseplate
102
. The spacers
130
maintain the orientation between baseplate
102
and faceplate
104
so that the baseplate and faceplate are substantially parallel to one another. Outer walls (not shown) seal the outer periphery of FED
100
and the space between baseplate
102
and faceplate
104
is substantially evacuated. Since the space between faceplate
104
and baseplate
102
is substantially evacuated, atmospheric pressure tends to press baseplate
102
and faceplate
104
together. However, spacers
130
resist this pressure and maintain the spacing between baseplate
102
and faceplate
104
.
FED
100
also includes a power supply
140
for (1) charging the transparent conductor
122
to a highly positive voltage; (2) charging the grid layer
112
to a positive voltage; and (3) selectively charging selective ones of the row and column lines
118
to a negative voltage.
In operation, voltages applied to the row and column lines
118
, the grid layer
112
, and the transparent conductor
122
cause emitters
108
to emit electrons
150
that travel along path
117
towards, and impact on, phosphor layer
124
. Incident electrons
150
on phosphor layer
124
cause phosphor layer
124
to emit photons and thereby generate a visible display on faceplate
104
.
The visible display of FED
100
is normally arranged as a matrix of pixels. Each pixel in the display is typically associated with a group of emitters
108
, with all the emitters
108
in a group being dedicated to controlling the brightness of their associated pixel. For example,
FIG. 1
shows a single pixel
160
, with pixel
160
being associated with emitters
108
a
,
108
b
,
108
c
, and
108
d
. Pixel
160
could be a single pixel of a black and white display or a single red, green, or blue dot associated with a single pixel of a color display. Charging line
118
a
to a negative voltage simultaneously activates emitters
108
a-d
causing emitters
108
a-d
to emit electrons that travel towards and impact on phosphor layer
124
in the region of pixel
160
. Normally, the row and column lines are arranged so that the emitters associated with one pixel can be controlled independently of all other emitters in the display and so that all emitters associated with a single pixel are controlled in unison.
The top of each spacer
130
contacts a portion of faceplate
104
. Electrons emitted by emitters
108
can not impact phosphor layer
124
in the regions where the spacers
130
touch the phosphor layer
124
. So, each spacer
130
creates a black, or dark, region of the display that can not be illuminated. The presence of dark regions created by spacers
130
does not significantly degrade the quality of the display of FED
100
as long as the area of the dark regions is small compared with the area of the illuminated pixels. Four or more spacers
130
are normally disposed around the periphery of each pixel. It is therefore important for the cross section of the spacers
130
to be relatively small compared with the area of each pixel. Ideally, the spacers
130
are characterized by a relatively high aspect ratio (i.e., the spacer's height is larger than its width). Such a high aspect ratio (1) does not create dark regions large enough to degrade the display quality and (2) provides sufficient spacing between the baseplate
102
and faceplate
104
to permit electrons traveling from emitters
108
towards faceplate
102
to acquire sufficient energy to cause phosphor layer
124
to emit photons. The spacers
130
must also provide sufficient structural strength to resist the atmospheric pressure and thereby maintain the desired spacing between baseplate
102
and faceplate
104
. It is also desirable for all spacers
130
to have exactly the same height so they can provide uniform spacing between the baseplate
102
and the faceplate
104
. It is also important for the spacers to be properly aligned with respect to the array of pixels so the dark regions created where the spacers
130
contact the faceplate do not interfere with the display (e.g., it is desirable for the bottom of the spacers
130
to contact the grid layer
112
at selected locations that are between the apertures
116
and are equidistant from all the adjacent emitters). Since the spacers
130
are disposed within a vacuum, it is also important for the spacers to be formed from a vacuum compatible material (e.g., a material that does not outgas significantly).
Prior art spacers
130
are typically constructed using glass posts. After the posts are prepared they are bonded to the grid layer
112
. Following this bonding, the faceplate
104
is fitted onto the posts. Functioning FEDs may be constructed using these techniques, however, these techniques have several disadvantages. For example, when the spacers are fabricated from glass posts, it is difficult to insure that every spacer has precisely the same height. Variation in spacer height degrades the parallel alignment between the faceplate and baseplate and thereby degrades the quality of the FED. Another problem with prior art spacer manufacturing techniques is that they do not permit precise alignment of the spacers with respect to the pixel array. As stated above, any deviation from the desired alignment can cause the dark regions created where the spacers contact the faceplate
104
to degrade the quality of the display. Ideally, the bottom of each spacer
130
contacts the grid layer
112
at a point that is equidistant from all the adjacent emitters, however, prior art spacer manufacturing techniques make it difficult to achieve this ideal. It would therefore be desirable to develop a new technique for fabricating spacers
130
for use in FEDs that provides improved control in manufacturability.
The use of porous, low-density xerogel materials for form
Hofmann James J.
Kraus Brenda D.
Vaartstra Brian A.
Westmoreland Donald L.
Chowdhury Tarifur R.
Wilmer Cutler Pickering Hale and Dorr LLP
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