Method for making single electrode U-MOSFET random access memory

Metal treatment – Process of modifying or maintaining internal physical... – Chemical-heat removing or burning of metal

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29571, 29580, 148175, 156643, 156649, 156653, 156662, 357 23, 357 41, 357 45, 357 49, 357 50, 357 55, 357 56, 357 59, H01L 2120, H01L 21302

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042525799

ABSTRACT:
A method for making highly dense, dielectrically isolated, U-shaped MOSFET. In a preferred method a monocrystalline silicon P substrate with a N+ layer thereon, a P layer on the N+ layer and a N+ layer on the P layer is provided. A pattern of U-shaped openings is formed in the body through to the P substrate by the reactively ion etching technique. This pattern of openings is filled with an insulator material, such as silicon dioxide. A conductive layer of N+ doped polycrystalline silicon is deposited on the bare surface of this silicon body. Openings are formed in the polycrystalline silicon over the silicon dioxide filled openings. A silicon dioxide layer is then grown by, for example, thermal oxidation over the polycrystalline silicon layer. Reactively ion etching is used to produce substantially U-shaped openings through the layers over the P substrate and into the P substrate to substantially bisect the regions of monocrystalline silicon. This etching step forms two storage cells in the monocrystalline silicon areas and a bit line for each column of cells in the polycrystalline silicon layer. A silicon dioxide gate insulator is grownon the monocrystalline silicon surfaces of the U-shaped openings by thermal oxidation in a suitable ambient. Conductively doped polycrystalline silicon is deposited in the U-shaped openings over the silicon dioxide gate insulator layer until the openings are filled and cover the surface of the body. The conductively doped polycrystalline silicon on the surface of the body is etched in a suitable pattern to produce the word lines of the random access memory device.

REFERENCES:
patent: 3412297 (1968-11-01), Amlinger
patent: 3938241 (1976-02-01), George et al.
patent: 3975221 (1976-08-01), Rodgers
patent: 4003126 (1977-01-01), Holmes et al.
patent: 4017883 (1977-04-01), Ho et al.
patent: 4037306 (1977-07-01), Gutteridge et al.
patent: 4044452 (1977-08-01), Abbas et al.
patent: 4070690 (1978-01-01), Wickstrom
patent: 4084175 (1978-04-01), Ouyang
patent: 4104086 (1978-08-01), Bondur et al.
patent: 4105475 (1978-08-01), Jenne
patent: 4116720 (1978-09-01), Vinson
patent: 4145703 (1979-03-01), Blanchard et al.
Rodgers, T. J., "VMOS Memory Technology" 1977, IEEE Int. Solid-State Circuits Conf., Digest of Tech. Papers, pp. 74, 75, 239.
Holmes, F. G., "VMOS-Bipolar Compatible-Integrated Circuits" IEEE Transactions on Electron Devices, Jun. 1977, pp. 771-773.

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