Method for making silicide interconnection structures for integr

Details Method for making silicide interconnection structures for integr Method for making silicide interconnection structures for integr

1988-11-08

1989-10-10

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437193, 437 34, 437 51, 437 56, 148DIG19, 148DIG147, 148DIG1, H01L 21283

Patent

active

048732044

ABSTRACT:
A method for forming a contact to a selective region of an integrated circuit characterized by the steps of: forming a layer of refractory metal over and around the selected region; forming a layer of amorphous silicon over the layer of refractory metal; patterning the amorphous silicon into an elongated strip which extends away from the selected region; annealing the integrated circuit to convert the strip of amorphous silicon into a silicide path; and removing the unreacted refractory metal. The method of the present invention can be used to extend a contact to the source, drain, or gate of a MOSFET from the top of an adjacent section of field oxide, and can also be used as a method for local interconnection of IC devices, such as CMOS devices.

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Ku, S. M., IBM Technical Disclosure Bulletin, vol. 22, No. 4, Sep. 1979, pp. 1487-1488.
Muranka, S. P., J. Vac. Sci. Technol., 17(4), Jul./Aug. 1980, pp. 752-792.
Schutz, R. J., et al., Appl. Phys. Lett., 34(1), Jun. 1, 1979, pp. 797-798.

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