Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2000-06-30
2002-09-10
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S238000, C438S239000, C438S243000, C438S244000, C438S692000
Reexamination Certificate
active
06448149
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for making shallow trench isolation (STI) to reduce the leakage current of the transistors and to achieve desired gap filling in semiconductor fabrication.
2. Description of the Related Art
When fabricating integrated circuits, individual devices such as transistors, diodes, resistors must be electrically isolated from one another. The semiconductor manufacturing process typically begins with the formation of isolation structures. The isolation formation procedure, thus, critically affects the sizes of the active regions and the process margin of subsequent processing.
One of a variety of technologies for forming the isolation structures is LOCOS (LOCal Oxidation of Silicon), which is generally employed for obtaining the device geometry of sub-half micron order. In a typical LOCOS isolation formation procedure, a pad oxide layer and a nitride layer are sequentially formed on a silicon substrate. Then the nitride layer is patterned. And the silicon substrate is selectively oxidized to form field oxide layers. Such LOCOS isolation inherently has the drawback called “bird's beak effect.” It is because oxidants laterally diffuse at the edges of the silicon nitride during the formation of the isolation structures. Thus, an oxide forms under the nitride edges and lifts the nitride edges. This lateral extension of the field oxide into the device active regions shortens the channel length. Thus, this phenomenon is called “narrow channel effect”, increasing the threshold voltage, thereby degrading the electrical characteristics of the transistors. Moreover, as the channel length is reduced below 0.3 &mgr;m, “punch-through” can occur. As a result, the active regions may not be properly secured.
Hence, the STI has been considered as a replacement for the conventional LOCOS for semiconductor devices having a design-rule of about 0.25 &mgr;m and under. Typically, the STI process begins with etching of trenches with a prescribed depth on a silicon substrate. Then an insulating layer is deposited over the substrate with the trenchs. The insulating layer is subject to etching-back or chemical mechanical polishing (CMP) process to finally have the trenches filled with the insulating layer.
Referring to
FIGS. 1
to
3
, which more specifically describe the STI, a pad oxide layer
11
, silicon nitride layer
12
, and a high temperature oxide layer (not shown) are sequentially deposited over a semiconductor substrate
10
. Then, the layers are partially removed over the regions for forming the trenches on the substrate by a photolithography-and-etch step, to form an active mask layer consisting of the high temperature oxide layer, silicon nitride layer
12
, and pad oxide layer
11
over the active regions. The active mask is used to etch the substrate
10
to form the trenches
14
with a predetermined depth. During the etching, the high temperature oxide layer is also removed, as illustrated in FIG.
1
.
An ozone-TEOS USG layer
16
is subsequently deposited over the silicon nitride layer
12
with a thickness sufficient to fill the trenches
14
, as shown in FIG.
2
. In order to reduce the surface tension of the oxide layer filling the trenches
14
and to tightly cover the trenches
14
, a capping oxide layer
20
is deposited over the ozone-TEOS USG layer
16
using the plasma-enhanced chemical vapor deposition (PE-CVD), as shown in FIG.
3
. After partially etching back the capping oxide layer
20
and ozone-TEOS USG layer
16
to reduce the surface level differences of the substrate, CMP is performed to remove the capping oxide layer
20
and ozone-TEOS USG layer
16
so as to expose the silicon nitride layer
12
, thereby forming the STI regions filled with planarized ozone-TEOS USG layer
16
.
However, as the aspect ratio of the tenches increases, the trenches are not often fully filled with the ozone-TEOs USG layer, creating voids
18
inside of the trenches. In addition, the quality of the ozone-TEOS USG layer is generally inferior to that if the thermally grown oxides.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for making the STI of a semiconductor device to reduce the leakage current of transistors.
It is another object of the present invention to provide a method for making the STI of a semiconductor device to achieve desired gap filling by reducing the aspect ratio of the trenches.
According to an aspect of the present invention, a method for making the STI (Shallow Trench Isolation) of a semiconductor device, comprises the steps of forming an active mask layer on a semiconductor substrate, etching the semiductor substrate, using the active mask layer as an etch mask, to produce a plurality of trenches, depositing an oxide layer by HDP-CVD (High Density Plasma Chemical Vapor Deposition) over the active mask layer so as to fill the trenches to a thickness greater than the depth of the trenches and less than the sum of the depth and the thickness of the active mask layer, depositing a capping oxide layer over the HDP-CVD oxide layer by means of plasma source of TEOS (Tetra-Ethyl-Ortho-Silicate), and polishing the capping oxide layer and HDP-CVD oxide layer so as to expose the active mask layer.
Preferably, the step of forming the active mask layer further includes the steps of forming a pad oxide layer over the semiconductor substrate, depositing a silicon nitride layer over the pad oxide layer, and depositing another oxide layer over the silicon nitride layer. The capping oxide layer is deposited with a thickness of 1000~5000 Å.
According to another aspect of the present invention, a method for making the STI of a semiconductor device, comprises the steps of forming an active mask layer on a semiconductor substrate, etching the active mask layer and semiconductor substrate to produce a plurality of trenches so as to form a first wide active mask region between two of the trenches and a second narrow active mask region between other two of the trenches, depositing an oxide layer by HDP-CVD over the active mask layer so as to fill the trenches, the thickness of the HDP-CVD oxide layer on the first wide mask region being greater than that on the second narrow mask region, depositing a capping oxide layer over the HDP-CVD oxide layer by means of plasma source of TEOS, partially etching back the capping oxide layer and HDP-CVD oxide layer on the first wide active mask region, and polishing the capping oxide layer and HDP-CVD oxide layer so as to expose the active mask layer.
Preferably, the step of partially etching back the capping oxide layer and HDP-CVD oxide layer further includes photolithography to open the first wide active mask region. The HDP-CVD oxide layer is deposited over the active mask layer so as to fill the trenches to a thickness greater than the depth of the trenches and less than the sum of the depth of the trenches and the thickness of the active mask layer.
According to still another aspect of the present invention, a method for making the STI of a semiconductor device comprises the steps of forming an active mask layer on a semiconductor substrate, etching the active mask layer and semiconductor substrate to produce a plurality of trenches, depositing an oxide layer by HDP-CVD over the active mask layer so as to partially fill the trenches to reduce the aspect ratio of the trenches, depositing an ozone-TEOS USG layer over the HDP-CVD oxide layer so as to the trenches, depositing a capping oxide layer over the ozone-TEOS USG layer by means of plasma source of TEOS, and polishing the capping oxide layer, ozone-TEOS USG layer and HDP-CVD oxide layer so as to expose the active mask layer.
Thus, the deposition of the capping oxide layer of PE-TEOS after filling the trenches with the HDP-CVD oxide layer results in improvement in the leakage current and refresh characteristics of the transistors. In addition, the ozone-TEOS USG layer is deposited t
Lee Seung-Jae
Lee Soo-Seun
Lim Hoon
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co Ltd.
Smith Matthew
Yevsikov V.
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