Method for making semiconductor integration circuit with stacked

Details Method for making semiconductor integration circuit with stacked Method for making semiconductor integration circuit with stacked

1991-04-10

1993-06-08

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 52, 437 60, 437919, H01L 2170, H01L 21265

Patent

active

052179141

ABSTRACT:
Disclosed is a semiconductor integrating circuit having stacked capacitor cells. Each of the cells includes an electric charge storage electrode for storing an electric charge, and a capacitor insulation film and opposite plate electrode integrated thereon. The electric charge storage electrode consists essentially of a bottom and a part in at least double frame-like portion or at least one column-like portion and at least one frame-like portion surrounding the column-like portion rising upwardly from the bottom surface. The capacitor deposited film consists of a dielectric material film deposited on all of the bottom plane and all surfaces of the charge storage electrode, and constructs a capacitor in cooperation with the opposite plate electrode. The described method for making a stacked capacitor cell can make it possible to form self-aligned capacitors by repeating a deposition of an oxide film and a conductive film and an anisotropic etching.

REFERENCES:
patent: 4742018 (1988-05-01), Kimura et al.
"A New Stacked Capacitor Cell for 64M Bit DRAMS" ESSDERC 90, Notingham, Sep. 1990, Section 6 A 1, by C. S. Kim et al.
"Stacked Capacitor Cell Technology for 16M Bit DRAMS" ESSDERC 90, Notingham, Sep. 1990, Section 6 A 1, by C. S. Kim et al.
"Stacked Capacitor Cell Technology for 16M DRAM Using Double Self-aligned Contacts" ESSDERC 90, Notingham, Sep. 1990, Section 6 A 2, by M. Fukumoto et al.
A 1.28 .mu.m.sup.2 Bit-Line Shielded Memory Cell Technology for 64 Mb DRAM IEEE Symposium on VLSI Technology (1990) by Y. Kawamoto et al.

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