Method for making semiconductor device with no stress generated

Details Method for making semiconductor device with no stress generated Method for making semiconductor device with no stress generated

1989-10-31

1991-01-15

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 52, 437 67, H01L 21265, H01L 2978, H01L 2996

Patent

active

049853686

ABSTRACT:
The semiconductor device in which no stress occurs at the corner portion of the trench comprises a p type semiconductor substrate having a trench and a main surface, a thick insulating film formed on the bottom portion of the trench, a thin insulating film formed on the sidewall portion of the trench and connected to the end portion of the thick insulating film, and an n type impurity region formed in the semiconductor substrate only on the side portion of the thin insulating film.

REFERENCES:
patent: 4611387 (1986-09-01), Soclof
patent: 4704368 (1987-11-01), Goth et al.
patent: 4740827 (1988-04-01), Niitsu et al.
patent: 4751557 (1988-06-01), Sunami et al.
patent: 4756793 (1988-07-01), Peek
patent: 4845048 (1989-07-01), Tamaki et al.
patent: 4859615 (1989-08-01), Tsukamoto et al.
Extended Abstracts of the 18th (1986 International) Conference on Solid State Devices and Materials, Tokyo, 1986, pp. 295-298.
"Peripheral Capacitor Cell with Fully Recessed Isolation for Megabit DRAM" by K. Tsukamoto et al.

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