Fishing – trapping – and vermin destroying
Patent
1995-10-30
1997-07-29
Chaudhari, Chandra
Fishing, trapping, and vermin destroying
437 56, 437157, H01L 21266
Patent
active
056521553
ABSTRACT:
A method for reducing encroachment of an impurity implant into a channel region in a non-ESD transistor in a semiconductor circuit, the non-ESD transistor receiving both first and second implant dopants, and the circuit including a plurality of ESD transistors includes forming the ESD transistors of the circuit at a predetermined angular offset from the non-ESD transistor, and performing the second dopant implant at a predetermined tilt implant angle, wherein the non-ESD transistor has reduced encroachment of the impurity implant. A plurality of transistors formed on a semiconductor wafer include a plurality of non-ESD transistors, the plurality of non-ESD transistors including spacer regions and impurity implant regions encroaching the spacer regions, and a plurality of ESD transistors, the plurality of ESD transistors formed at a predetermined angular offset from the non-ESD transistors. Further, the plurality of ESD transistors include the spacer regions and impurity implant regions encroaching the spacer regions further than the impurity implant regions of the non-ESD transistors.
REFERENCES:
patent: 5040035 (1991-08-01), Gabara et al.
patent: 5406111 (1995-04-01), Sun
patent: 5496751 (1996-03-01), Wei et al.
Chang Chi
Kwan Ming Sang
Liu David K. Y.
Advanced Micro Devices , Inc.
Chaudhari Chandra
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