Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-07-01
2003-02-18
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C720S723000, C720S724000, C720S745000, C720S724000, C720S724000, C720S724000, C720S724000
Reexamination Certificate
active
06521540
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the formation self-aligned contacts to source/drain regions, next to polysilicon gate structures, that allows for “zero” spacing from contact structure to gate structure, without requiting the use of an insulating hard mask layer over the poly gate. The process is very useful for the “standard” logic device salicided processes.
As transistor dimensions approached sub-micron, the conventional contact structures start to limit device performance in several ways. First, it becomes difficult to minimize contact resistance when the contact hole opening is of minimum size-and also problems with cleaning small contact holes become a concern. In addition, with defined conventional contacts, the area of the source/drain regions cannot be minimized because the contact hole has be aligned to these regions with a separate masking step, and a large “extra” area has to be allocated for possible misalignment. Furthermore, this larger “extra” area also results in increased source/drain-to-substrate junction capacitance, which impacts device speed. Finally, when conventional width MOSFET's are fabricated with conventional contacts, several small, uniformly sized contact holes have to be used, rather than one wider contact hole. The main reason for this is that being of same size, the contact holes will to be opened simultaneously during the etching process. Using several small, equally sized contact holes rather than one wider one, wastes valuable space and the full width of the source/drain region is not fully utilize. Hence, the conventional device contact resistance is larger than it could have been in a device having minimum width. Self-aligned contact process schemes solve many of the micron and sub-micron CMOS MOSFET contact problems, easing both the device ground rule designs and easing the processing problems associated with convention contacts. The self-aligned contacts makes better use of the space and area over the source/drain region, as will be described in more detail.
In CMOS process technology, metal contacts for the source and drain electrical connection must have some distance or space away from the polysilicon gate to avoid electrically short circuiting the metal contact to the gate electrode. This spacing requirement restricts the product chip density in the design groundless, especially for memory chip technologies. The self-aligned process can be developed to allow “zero” spacing from the contact to source/drain to the gate. The standard or conventional self-aligned contact process utilizes a insulator capped polysilicon for the gate structure. The insulating layer, sometimes referred to as the “hard mask”, can either be a conformal layer of silicon nitride or a conformal layer of silicon oxide. This standard SAC, self-aligned contact process works well for the Polycide process (Polycide structure: gate oxide/polysilicon gate/metal silicide) however, this process is not compatible with the Salicide process, self-aligned silicide due to the presence of the insulating layer over the poly gate. Therefore, in order to make the SAC process simple and compatible with the Salicide process, the a SAC process needs to be formulated without the use of the conventional conformal insulating layer over the polysilicon gate structure. As will be shown later in this invention, this invention describes a self-aligned source/drain contact process that allows for “zero” spacing between the source/drain contact to the gate, without requiring the use of an insulator layer on top of the polysilicon gate structure. As will be described later, the process described in this invention is completely compatible with both the state of-the-art current Salicide processing, as well as, the state of-the-art Polycide processing, with improved device electrical performance, improved design groundrules, and improved device reliability.
(2) Description of Related Art
In the fabrication of semiconductor integrated circuits the method of forming SAC, self-aligned contacts to. source/drain regions in the fabrication of CMOS MOSFET's can be used to advantage to improve chip design ground rules, improve contact reliability, and improved device performance. In some cases, these self-aligned process schemes are merged with shallow trench isolation (STI) schemes. This section contains pertinent PRIOR ART patents and are meant to provide some processing background for the present invention.
U.S. Pat. No. 5,731,241 entitled “Self-Aligned Sacrificial oxide for Shallow Trench Isolation” granted Mar. 24, 1998 to Jang et al describes a method of forming a sacrificial self aligned sub-atmospheric chemical vapor deposition (SACVD) ozone-TEOS tetra-ethyl-ortho-silicate layer over a trench oxide. This layer protects the trench oxide and is preferentially deposited over the trench oxide rather than over the thermally grown pad oxide. Two preferred embodiments are presented: (1) a first self aligned sacrificial ozone-TEOS layer over the trench before the pad oxide etch, and (2) a second self-aligned sacrificial ozone-TEOS layer deposited before the sacrificial ion implant oxide etch. The protecting ozone-TEOS film layer can be applied in a variety of process situations in shallow trench isolation (STI), where it protects the trench oxide from etch damage.
U.S. Pat. No. 5,817,562 entitled “Method for Making Improved Polysilicon FET Gate Electrode Structures and Sidewall Spacers for More Reliable Self-Aligned Contacts (SAC)” granted Oct. 6, 1998 to Chang et al shows a method of forming FET stacked gate electrode structures with improved sidewall profiles. The more vertical sidewalls improve the control tolerance of the gate electrode effective length and improve the shape of the sidewall spacers for making more reliable metal contacts to self-aligned source/drain contact areas. The method employs the use of a stacked gate electrode layer having a tetra-ethyl-ortho-silicate (TEOS) oxide and a hard mask of silicon nitride on the gate electrode polysilicon layer. This stacked gate structure is used during patterning and prevents a buildup of polymer on the sidewall. The end result is improved gate line length tolerance, improved gate sidewall spacers, that minimize shorts between metal source/drain contacts and the polysilicon gate electrodes.
U.S. Pat. No. 5,480,814 entitled “Process of Making a Polysilicon Barrier Layer in a Self-Aligned Contact Module” granted Jan. 2, 1996 to Wuu et al shows a method of forming a metal contact in a self aligned contact region over an impurity region in a substrate. A doped polysilicon layer is formed over the device surface except in a contact area. A thin polysilicon barrier layer and a metal layer are then formed over the poly layer and the contact area. The resulting metal contact structures are reported to have superior step coverage, lower resistivity, and maintains the shallow junction depth of buried impurity regions.
The present invention is directed to a novel method of forming self aligned metal electrical contacts to source/drain areas allowing for “zero” spacing between the contact and gate area and a summary of the main embodiments of the present invention follows.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a new and improved method of forming an integrated circuit in which the fabrication of self aligned metal contacts to source/drain area is described, in the manufacture of CMOS MOSFET devices. As a background to the present invention, reference is first made to conventional Prior Art methods.
The standard or conventional Prior Art method for fabricating metal self-aligned contact to source/drain area consists of the follow process steps. Provided are the following layers and structures comprising: substrate of single crystal silicon semiconductor, source/drain contact region over source/drain ion implantation/diffusion area, FET gate oxide, gate elect
Brown Charlotte A.
Chartered Semiconductor Manufacturing Ltd.
Pike Rosemary L. S.
Saile George O.
Utech Benjamin L.
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