Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2000-09-29
2002-02-26
Fabmayl, Wael (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S755000, C257S756000, C257S757000, C439S649000, C439S672000
Reexamination Certificate
active
06351037
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a method of making polycide-to-polycide contacts for multilevel interconnections on semiconductor integrated circuits, and more particularly relates to a method and structure for forming low-resistance contacts between interconnecting polycide layers.
(2) Description of the Prior Art
Advances in semiconductor processing technologies, such as advances in high-resolution photolithography and anisotropic plasma etching, continue to reduce the feature sizes of semiconductor devices. These reduced feature sizes include smaller contact openings leading to higher contact resistance. For example, current contact opening feature sizes are now typically less than 0.5 micrometer (um). The increase in this parasitic resistance in series with circuit devices, such as field effect transistors (FETs), degrade the circuit performance and therefore is undesirable. A further concern is wide distribution in contact resistance (R
c
), which is also undesirable.
It is common practice in the semiconductor industry to interconnect the semiconductor devices by using multilayers of patterned heavily doped polysilicon/silicide layers, commonly referred to as polycide layers, and by metal layers to form the integrated circuits. Interlevel dielectric (ILD) layers, hereafter referred to as “insulating layers,” having contact openings (via holes) between the polycide layers are used to electrically insulate the various polycide and metal layers on the substrate. On Ultra Large Scale Integration (ULSI) the number of contacts now well exceeds a million and it is important to have consistently low contact resistance (R
c
) from contact to contact.
One method of providing consistently low contact resistance between aluminum metal levels, by the prior art, is to in-situ sputter clean the contact openings just prior to physical vapor depositing the next level of aluminum to avoid the aluminum oxide formation that readily forms during exposure to the ambient. Unfortunately, this requires retrofitting the deposition tool with a sputtering system and further complicates the process.
High contact resistance problems are also a concern between silicide/polysilicon (polycide) to silicide/polysilicon (polycide) layers that are also typically used to form part of semiconductor devices such as FET gate electrodes, word lines. bit lines, etc. on integrated circuits, such as dynamic random access memory (DRAM), static random access memory (SRAM), and microprocessors. A typical prior art contact between two tungsten silicide/polysilicon patterned layers is shown in FIG.
1
. The contact structure is shown built on a semiconductor substrate
10
having an insulating layer
12
thereon. Shown is a first polycide layer composed of a first polysilicon layer
14
and a first silicide layer
16
comprised, in part, by the gate electrodes for an FET. The first polycide layer is then electrically insulated by depositing an insulating layer
20
, for example, by a chemical vapor deposited (CVD) oxide. The contact openings
4
are then formed in the insulating layer
20
to the surface of the first silicide layer
16
by using conventional photolithographic techniques and anisotropic plasma etching. Still referring to
FIG. 1
, an undoped second polysilicon layer
21
is deposited over the insulating layer
20
, and in the contact openings for making contact with the top surface of the first silicide layer
16
. A doped polysilicon layer
24
is deposited on the undoped polysilicon layer
21
. The undoped polysilicon layer
21
is used to prevent diffusion of dopants from polysilicon layer
24
into the substrate
10
when the contact is made over the cell contact regions (N
−
), such as FET source/drain regions, to prevent deep junctions from forming. The second level of interconnecting metallurgies is now completed by depositing a second silicide layer
26
. Layers
26
,
24
, and
21
are then patterned using conventional photolithographic and plasma etching to form the second patterned conducting layer.
Unfortunately, it is difficult to form consistently low contact resistance for the contacts, as in
FIG. 1
, because of the difficulty in removing residual polymers that occur during the etching of the contact openings, such as opening
4
in
FIG. 1
, and the subsequent removal of the photoresist contact mask. For example, contacts having minimum feature sizes of 0.5 um or less can have contacts with resistance that varies from as low as 100 ohms to values exceeding 2000 ohms. Furthermore, interface treatments, such as plasma etching in a gas mixture containing CH
4
and O
2
to treat the tungsten silicide surface, are not effective, even when portions of the top surface of the silicide layer
16
are partially removed. Alternatively, implant doping of the tungsten silicide layer
16
in the contact openings does not provide consistently low contact resistance.
Therefore, there is still a strong need in the semiconductor industry to further provide methods for forming contacts with low contact resistance for these interconnecting metallurgies, while eliminating the need for additional processing steps to reduce the resistance, and thereby providing a more cost-effective manufacturing process.
SUMMARY OF THE INVENTION
It is therefore a principal object of the present invention to provide a method and structure for forming electrical contacts between polycide layers having repeatable low contact resistance (R
c
).
It is another object of this invention to provide the above structure while reducing the process complexity and thereby providing a more cost-effective manufacturing process.
In accordance with the above objectives, by a first embodiment, a method and a resulting structure for an electrical contact between patterned polycide layers having low contact resistance (R
c
) for interconnections on integrated circuits are described. The method begins by providing a semiconductor substrate, such as single-crystal silicon wafers, having field oxide (FOX) regions surrounding and electrically isolating device areas. The most commonly used FOX is formed by the method of LOCal Oxidation of Silicon (LOCOS), in which a patterned silicon nitride layer over the device areas is used as a barrier to oxidation. The silicon substrate is thermally oxidized in the exposed field oxide areas to form a relatively thick silicon oxide (SiO
2
). A first polysilicon layer is deposited on the substrate after forming a thin gate oxide in the device areas, and the polysilicon layer is N
+
doped making it electrically conducting. A first silicide layer, such as tungsten silicide, is then deposited on the first polysilicon layer to form a polycide layer that further improves the conductivity. The polycide (polysilicon/silicide) layer is now patterned by using a photoresist mask and anisotropically etching to form, for example, FET gate electrodes over the device areas, and concurrently provide polycide interconnecting metallurgy over the field oxide regions. Although the method is described for making contacts to a first polycide layer used for FET gate electrodes, it should be well understood by those skilled in the art that the method is generally applicable to making low contact resistance contacts between any two polycide layers on the substrate. Typically after forming the gate electrodes, other process steps are employed to complete the FET. For example, forming lightly doped drains (LDD) by ion implantation, forming insulating sidewall spacers by anisotropically etching back, for example, a silicon oxide layer (CVD oxide) deposited over the gate electrodes, and then forming heavily doped FET source/drain contact areas. These process steps are carried out as commonly practiced in the industry and are not described in further detail to simplify the discussion of the invention.
Continuing with the invention, an insulating layer is deposited over the patterned first polycide layer to insulate the first polycide layer from the next level of interconnectio
Cherng Meng-Jaw
Liaw Ing-Ruey
Ackerman Stephen B.
Brewster William M.
Fabmayl Wael
Saile George O.
Vanguard International Semiconductor Corporation
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