Method for making passivated mesa semiconductor

Details Method for making passivated mesa semiconductor Method for making passivated mesa semiconductor

1992-07-29

1994-01-11

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437952, 437956, H01L 2122

Patent

active

052780953

ABSTRACT:
A process for forming a semiconductor device begins by diffusing an N layer having a relatively high concentration into a P wafer having a relatively low concentration. Next, the wafer is etched to yield a plurality of mesa semiconductor structures, each having a P-N junction intersecting a sidewall of the mesa structure. Then, a layer of oxide is grown on the sidewalls of the mesas, which oxide layer passivates the device. The oxidizing step curves the P-N junction toward the P layer in the vicinity of the oxide layer. Then, the P-N junction is diffused deeper into the P layer with a diffusion front which tends to curve the P-N junction back toward the N layer in the vicinity of the oxide layer. This diffusion is carried out to such an extent as to compensate for the curvature caused by the oxidizing step and thereby substantially flatten the P-N junction. A plurality of successive oxidation/diffusion steps can be undertaken to further flatten the junction adjacent the mesa sidewall. The resultant P-N junction has a greater breakdown voltage in the vicinity of the oxide layer due to the substantial flatness of the P-N junction. The decreased concentration gradient of the linearly graded junction in the vicinity of the oxide layer caused by the oxidizing step increases the breakdown voltage in the vicinity of the oxide layer above the bulk breakdown voltage.

REFERENCES:
patent: 3832246 (1974-08-01), Lynch
patent: 4210472 (1980-07-01), Hoffman et al.
patent: 4740477 (1988-04-01), Einthoven et al.
patent: 4757031 (1988-07-01), Kuhnert et al.
patent: 4980315 (1990-12-01), Einthoven et al.

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