Radiation imagery chemistry: process – composition – or product th – Including control feature responsive to a test or measurement
Reexamination Certificate
1999-10-13
2001-08-21
Young, Christopher G. (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Including control feature responsive to a test or measurement
C430S005000, C430S296000
Reexamination Certificate
active
06277530
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a method for making a partial full-wafer pattern for charged particle beam lithography, and more particularly to, a method for making a partial full-wafer pattern that allows a pattern to be transferred at severer size accuracy.
BACKGROUND OF THE INVENTION
According as the integration density of LSI increases, for the exposure of a fine pattern less than a limitation of optical resolution, instead of photolithography, the lithography using charged particle beam, i.e. electron beam and X-ray, begins to be used.
The charged particle beam lithography using charged particle beam, i.e. electron beam lithography using electron beam, is a technique that a fine pattern less than a limitation of optical resolution is transferred onto a transferred medium using electron beam. Conventionally, such a pattern is written directly onto a substrate by the single-stroked drawing using variable shaping electron beam.
The single-stroked drawing i s a method that a pattern of LSI circuit to be written is divided to a size of variable shaping electron beam and part divided is written by using electron beam. It is called variable shaping method. For example, in writing a pattern of LSI circuit a rectangular beam divided into such a shot size that all patterns composing the LSI circuit can be exposed is used in the multiple exposure shots.
However, in the variable shaping method, as the pattern to be written becomes fine, the number of shots increases rapidly. Therefore, the throughput reduces significantly.
Since the throughput of the variable shaping method is thus low, in the field of electron beam lithography, in recent years, used is a so-called partial full-wafer electron beam exposure method that uses a transfer mask for the exposure of electron beam with a desired pattern, like the transfer method by light or X-ray using a mask or a reticle, to enhance the throughput and a repeated pattern is exposed sequentially by electron beam. For example, a pattern requiring 40 to 80 shots in the conventional variable shaping method can be exposed by one shot.
A repeated pattern to be exposed in the partial full-wafer electron beam exposure method is generally called a partial full-wafer pattern. In general, the size of partial full-wafer pattern only has to be smaller than a maximum exposable region that can be exposed by the single partial full-wafer electron exposure. The mask pattern for partial full-wafer pattern is formed, as abored hole with an analogous shape to the repeated pattern, on a transfer mask for partial full-wafer electron exposure.
In making a bored hole on the mask, pattern data for mask pattern to each partial full-wafer pattern is made based on pattern data for partial full-wafer pattern, and then the bored hole is formed on the mask based on that data using an electron beam lithography system.
The mask for partial full-wafer electron beam exposure is generally provided with multiple mask patterns for partial full-wafer pattern and at least one mask pattern for variable shaping.
The partial full-wafer electron beam exposure method is a method that a stencil mask including a mask pattern formed with a bored hole is disposed between the electron gun and the substrate and the mask pattern is transferred onto the substrate by one-time electron beam exposure.
For example, most regions of memory circuit are composed of repeated unit patterns with a certain shape called a cell. A group of unit patterns are formed, as a partial full-wafer pattern, on the mask, and by conducting the electron beam exposure using this mask, a group of cells can be transferred onto the substrate by one shot.
Here, referring to
FIG. 1
, explained briefly is the partial full-wafer electron beam lithography system for conducting the partial full-wafer electron beam exposure.
As shown in
FIG. 1
, the partial full-wafer electron beam lithography system
50
generally comprises an electron gun
52
, a rectangular beam shaping system
54
composed of lenses and an aperture to shape electron beam emitted from the electron gun
52
into rectangular form, a deflector
56
to deflect rectangular electron beam so as to be projected on a desired mask pattern of the partial full-wafer pattern mask below, a partial full-wafer patterning system
60
provided with lenses and a partial full-wafer transfer mask
58
to pattern rectangular electron beam into a partial full-wafer pattern, and a projection system
62
composed of a demagnification projection lens and a deflector to project the partial full-wafer pattern on a wafer W.
Multiple mask patterns for partial full-wafer pattern -are formed on one partial full-wafer transfer mask
58
, and the higher the selection priority of mask pattern for partial full-wafer pattern is, the closer to the center it is disposed. Also, the partial full-wafer transfer mask
58
is provided with an opening with a large numerical aperture to be used as a mask pattern for variable forming.
To perform the partial full-wafer electron beam exposure, it is necessary to make a partial full-wafer pattern based on the circuit design data. For that purpose, the data processing system is provided as part of the partial full-wafer electron beam exposure system, or as a separate system from the partial full-wafer electron beam exposure system.
As shown in
FIG. 2
, the data processing system makes mask data and exposure data from the circuit design data of IC circuit, outputting them. Namely, the data processing system makes the exposure data by the data processing of the circuit design data of IC circuit, outputting it to the electron beam exposure system. Also, it conducts the extraction processing of partial full-wafer pattern from the circuit design data of IC circuit to extract a partial full-wafer pattern, making mask data by the data processing of the partial full-wafer pattern data extracted, outputting it to the mask fabrication system.
The mask data is data for fabricating a mask pattern on the transfer mask based on a partial full-wafer pattern extracted.
The exposure data is data necessary to expose it using the electron beam lithography system, data to indicate the position of pattern in the chip, for example, for a partial full-wafer pattern, data to indicate the position of exposure on the wafer, identification number, which position on the mask the partial full-wafer pattern with that identification number locates at etc. Also, for a variable shaping pattern, it is data to indicate the position of exposure, the size, the code of shape etc.
All of these data are extracted automatically from the circuit design data by the data processing system, then processed.
In conducting the partial full-wafer electron beam exposure, it may be imagined that a repeated pattern (unit pattern) only has to be predetermined as a partial full-wafer pattern. However, in this case, the designer of circuit must be restricted by the shape of unit pattern (repeated pattern) predetermined, therefore the degree of freedom in the designing of circuit must be lost. Therefore, such an optimum circuit designing that allows a desired characteristic to a semiconductor device becomes difficult.
So, in order to obtain the flexibility of circuit designing, it is necessary to extract a partial full-wafer pattern from the circuit design data of a pattern designed freely while taking the repetition into account. Also, in order to conduct the partial full-wafer electron beam exposure effectively, it is necessary to extract the partial full-wafer pattern so that the number of shots is minimized.
This is the extraction processing of partial full-wafer pattern mentioned earlier, and is conducted automatically with the processing to make the exposure data from the circuit design data by the data processing system.
The extraction of partial full-wafer pattern is conducted for circuit data after undergoing the overlap processing or process margin processing.
In the extraction processing of partial full-wafer pattern, at first, repeated patterns are extracted from the circuit data, wi
NEC Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
Young Christopher G.
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