Metal treatment – Compositions – Heat treating
Patent
1978-05-26
1979-03-20
Rutledge, L. Dewayne
Metal treatment
Compositions
Heat treating
148187, 357 23, 357 91, H01L 2126, H01L 21265
Patent
active
041452330
ABSTRACT:
A method for making an FET comprising as many as three parallel channels having different threshold voltages. The two outer channels can have very low W/L ratios and resulting low drain-to-source currents. In one embodiment, the FET has a central enhancement channel flanked by low W/L ratio, low current, depletion channels. This FET is fabricated by (1) forming on the field oxide a photoresist mask having a relatively narrow aperture; (2) overetching the field oxide beneath the photoresist mask aperture to form a relatively wide aperture in the field oxide, leaving a photoresist overhang; (3) implanting the substrate through the relatively narrow photoresist mask aperture to provide an enhancement section of the channel region; (4) removing the photoresist mask; and (5) depletion implanting the substrate through the relatively wide field oxide aperture. The gate structure is formed over the combined enhancement and depletion channels and a source and a drain span the ends of the channels. This effectively provides an enhancement FET which is in parallel with a depletion FET. The effective channel width of the depletion FET approximates the combined width of the two narrow depletion regions and is controlled by the photoresist overhang, i.e., by the relative width dimensions of the two mask apertures. The method is applicable to both silicon and metal gate technology, to n-channel and p-channel, and to various combinations of enhancement and/or depletion devices.
REFERENCES:
patent: 3863330 (1975-02-01), Kraybill et al.
patent: 3873372 (1975-03-01), Johnson
patent: 3883372 (1975-05-01), Lin
patent: 3933529 (1976-01-01), Goser
patent: 3996655 (1976-12-01), Cunningham et al.
patent: 4001860 (1977-01-01), Cauge et al.
patent: 4037307 (1977-07-01), Smith
patent: 4038107 (1977-07-01), Marr et al.
patent: 4078947 (1978-03-01), Johnson et al.
patent: 4084987 (1978-04-01), Godber
patent: 4089712 (1978-05-01), Joy et al.
Abbas et al, "Short Channel FET", IBM-TDB, 17 (1975), 3263.
Gdola, "Reducing Hot Carrier Injection . . .", IBM-TDB, 18 (1975), 1860.
Jones Robert K.
Sefick Stephen A.
Bergstedt Lowell C.
Cavender J. T.
Dalton, Jr. Philip A.
NCR Corporation
Roy Upendra
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