Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Insulative housing or support
Reexamination Certificate
2002-03-19
2003-08-05
Talbott, David L. (Department: 2827)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Insulative housing or support
C438S106000, C438S109000, C438S125000
Reexamination Certificate
active
06602739
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to high density interconnect (HDI) arrangements for electronic modules, and more particularly to methods for fabrication of such modules.
BACKGROUND OF THE INVENTION
High density interconnect assemblages such as those described in U.S. Pat. No. 4,783,695, issued Nov. 8, 1988 in the name of Eichelberger et al., and in numerous other patents, are finding increased usage. In one type of HDI assemblage, a dielectric substrate such as alumina has a planar surface defining one or more wells or depressions. Each well or depression extends below the planar surface by the dimension of a component which is to become part of the HDI assemblage. The component is typically an integrated circuit, having its electrical connections or contacts on an upper surface, but other components can be used. Each component is mounted in a well dimensioned to accommodate the component with its electrical contacts in substantially the same plane as the planar surface of the substrate. The components are typically held in place in their wells or depressions by an epoxy adhesive. A layer of dielectric material such as Kapton polyimide film, manufactured by DuPont of Wilmington, Del., is laminated to the devices using ULTEM polyetherimide thermoplastic adhesive, manufactured by General Electric Plastic, Pittsfield, Mass., which is then heat-cured at about 260° to 300° C. in order to set the adhesive. The polyetherimide adhesive is advantageous in that it bonds effectively to a number of metallurgies, can be applied in a layer as thin as 12 micrometers (&mgr;m) without formation of voids, and is a thermoplastic material, so that later removal of the polyimide film from the components is possible for purposes of repair by heating the structure to the plastic transition temperature of the polyetherimide while putting tension on the polyimide film.
Following the curing of the ULTEM adhesive layer holding the first sheet of dielectric film onto the components, through via apertures are laser-drilled through the dielectric film and its adhesive layer at the locations of at least some of the electrical connections. A patterned layer of titanium/copper/titanium electrical conductors is applied in a pattern to the exposed surface of the polyimide film, into the through vias, and onto the contacts of the components. This completes the formation of a first layer of electrical connections to the components. One or more additional thin sheets of polyimide dielectric material are layered onto the upper surfaces using silicone polyimide epoxy adhesive (SPIE). The SPIE is a thermoset material such as OXYSIM 600, manufactured by Occidental Chemical Corporation, Grand Island, N.Y., which is then cured at temperatures below 200°. Once set, the SPIE cannot be softened by heating. Each additional layer of polyimide film has its own pattern of through vias drilled as far as the upper titanium surface of a lower layer of titanium/copper/titanium conductor, followed by its own layer of titanium/copper/titanium deposition.
Alternative methods for making HDI modules include the “chip-on-flex” method, in which the solid-state chips are applied, electrode-side-down, onto an adhesive-faced dielectric layer. The chips are then encapsulated in a rigid molding material, which in one embodiment is Plaskon, an epoxy material, to form a rigid molded-chip-plus-dielectric-sheet piece. The flexible, multilayer interconnect sheet is then placed over the bottom of the dielectric sheet, which is to say on the side remote from the molding material, and the interconnections are made by means of laser-drilled vias.
SUMMARY OF THE INVENTION
Thus, a method according to an aspect of the invention is for generating a multi-chip module. The method comprises the steps of procuring a dielectric sheet defining a surface and tensioning the dielectric sheet, as by use of a frame, to provide a measure of rigidity to the surface. One or more electrical conductors is applied to the surface of the dielectric sheet in a predetermined pattern. The electrical conductors have a predetermined thickness. In one embodiment of the invention, the thickness is 40 thousandths of an inch, and the surface of the dielectric sheet is coated with adhesive to retain the conductors. Encapsulating material is applied to the surface of the dielectric sheet in a thickness sufficient to encapsulate the electrical conductors, to thereby generate a rigid substrate element. Wells or apertures, which may be through apertures, are fabricated, formed or defined in the rigid substrate element at predetermined locations at which semiconductor or solid-state chips are to be placed in or on the multi-chip module. The semiconductor or solid-state chips are placed on a second dielectric sheet or substrate at locations registered with the apertures or through apertures, with electrical pads, electrodes, or interconnects of the chips facing in a particular direction. In a particular embodiment of the invention, the second dielectric sheet has adhesive on one of its surfaces, and that side of the semiconductor or solid-state chips having electrical connection pads or electrodes of the semiconductor or solid-state chips are placed on the adhesive of the second sheet. The rigid substrate element with apertures is affixed to the second dielectric sheet with the semiconductor or solid-state chips extending into or through the wells or apertures. A flexible multilayer dielectric interconnection sheet carrying interconnection conductor patterns is formed on, andor applied over, at least the electrical connection pads or electrodes of some of the semiconductor or solid-state chips, for making connections between at least some of the interconnection conductor patterns of the interconnection sheet and some of the electrical connection pads. In a particular embodiment of the invention, the connections are made with the aid of plated-through vias.
In one variant of the method, a layer of encapsulant material is removed, shaved or ground from at least one surface of the rigid substrate element before the step of affixing the rigid substrate element to the second dielectric sheet. In another variant, the step of applying to the surface of the dielectric sheet, in a predetermined pattern, one or more electrical conductors having a predetermined thickness includes the step of applying adhesive to the surface of the dielectric sheet, and applying the one or more electrical conductors to the adhesive. In another mode of the method of the invention, an electrically conductive plate is affixed to the rigid substrate element on that side of the multichip module remote from the flexible multilayer dielectric interconnection sheet.
According to an aspect of the invention, the gaps between the rigid substrate element and the semiconductor or solid-state chips or other components and the associated wells or apertures are filled with a hardenable (curable) filler material. The filling may be accomplished by means of manually operated tools or by means of automatic or programmed dispensing machines.
REFERENCES:
patent: 4783695 (1988-11-01), Eichelberger et al.
patent: 5324687 (1994-06-01), Wojnarowski
patent: 5373627 (1994-12-01), Grebe
patent: 5492586 (1996-02-01), Gorczyca
patent: 5866952 (1999-02-01), Wojnarowski et al.
patent: 6429045 (2002-08-01), Furukawa et al.
Balch Ernest Wayne
Durocher Kevin Matthew
Gorczyca Thomas Bert
Kapusta Christopher James
Rose James Wilson
Duane Morris LLP
Lockheed Martin Corporation
Talbott David L.
Zarneke David A.
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