Fishing – trapping – and vermin destroying
Patent
1993-10-18
1995-06-27
Chaudhari, Chandra
Fishing, trapping, and vermin destroying
437 51, 437922, H01L 21441
Patent
active
054279798
ABSTRACT:
A multilevel antifuse structure characterized by a substrate, a first antifuse structure formed above the substrate, and a second antifuse structure formed above the first antifuse structure. The first antifuse structure preferably includes a first conductive layer, a first antifuse layer disposed over the first conductive layer, a first dielectric layer disposed over the first antifuse layer and provided with a first via hole, and a first conductive via formed within the first via hole. The second antifuse structure preferably includes a second conductive layer, a second antifuse layer disposed over the second conductive layer, a second dielectric layer disposed over the second antifuse layer and provided with a second via hole, and a second conductive via formed within the second via hole. Preferably, the first antifuse layer and the second antifuse layer are patterned into a plurality of antifuse regions which are either vertically aligned or vertically staggered with respect to each other. A method for making a multilevel antifuse structure in accordance with the present invention includes the steps of forming a first antifuse structure over a substrate, and forming a second antifuse structure over the first antifuse structure. In one embodiment, the first antifuse structure and the second antifuse structure are vertically aligned, and are interconnected in parallel. The parallel interconnection is preferably accomplished by tungsten vias formed by either a blanket tungsten deposition and subsequent etch-back, or by a selective tungsten deposition.
REFERENCES:
patent: 5070384 (1991-12-01), McCollum et al.
patent: 5106773 (1992-04-01), Chen et al.
patent: 5248632 (1993-09-01), Tung et al.
An FPGA Family Optmized for High Densities and Reduced Routing Delay, Ahrens et al., IEEE 1990 Custom Integrated Circuits Conference, 1990.
Chaudhari Chandra
VLSI Technology Inc.
LandOfFree
Method for making multi-level antifuse structure does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for making multi-level antifuse structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for making multi-level antifuse structure will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-287181