Method for making mask aligned narrow isolation grooves for a se

Details Method for making mask aligned narrow isolation grooves for a se Method for making mask aligned narrow isolation grooves for a se

1982-09-24

1984-08-07

Roy, Upendra

Metal working

Method of mechanical manufacture

Assembling or joining

29576W, 29571, 148 15, 156628, 156643, H01L 2122, H01L 21316

Patent

active

044634935

ABSTRACT:
A method for making mask aligned narrow isolation grooves for a semiconductor device in which an insulating layer is filled in a groove of the semiconductor substrate to form an island region surrounded by the insulating layer, which comprises the steps of forming a mask pattern on a major surface of the semiconductor substrate in such a manner that its side wall is at a taper angle of 90.degree. or less with respect to a major surface of the semiconductor substrate; ion-implanting an impurity of a conductivity type opposite to that of the semiconductor substrate into the semiconductor substrate using the mask pattern; causing a groove for the insulating material to be formed in the semiconductor substrate around the side wall of the mask pattern; filling the groove with insulating material to form a narrow insulating layer; and diffusing the implanted impurity to form an isolation region surrounded by the insulating material.

REFERENCES:
patent: 4053349 (1977-11-01), Simko
patent: 4135954 (1979-01-01), Chang et al.
patent: 4274909 (1981-06-01), Venkataraman et al.
patent: 4333794 (1982-06-01), Beyer et al.
patent: 4362597 (1982-12-01), Fraser et al.
patent: 4390393 (1983-06-01), Ghezzo et al.
Japanese Patent Disclosure (Kokai), No. 55-154748 and 55-154770, Y. Nagakubo, (May 23, 1979).

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