Method for making low leakage polycrystalline silicon-to-substra

Details Method for making low leakage polycrystalline silicon-to-substra Method for making low leakage polycrystalline silicon-to-substra

1981-09-14

1983-08-09

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

29591, 148187, H01L 2122, H01L 21265

Patent

active

043970761

ABSTRACT:
A process for making buried contacts without damaging the surface of the silicon substrate while etching the pattern of a poly interconnect layer. The contact cut made in the gate oxide layer covering the substrate is made smaller than the poly deposited and patterned thereover. Damage to the substrate surface during the etching of the poly layer pattern is prevented by the presence of the gate oxide layer between the poly layer and the substrate. An ion implantation step performed early in the process forms a parasitic depletion mode channel under the region having an overlap of poly onto gate oxide. Consequently, though the gate oxide prevents the direct diffusion of dopant into the underlying substrate when conductors are formed by doping, the parasitic channel ohmically couples the poly interconnect layer to the diffused region in the substrate. The latter region is usually the S/D electrode of an IGFET. The composite process is compatible with the formation of self-aligned gates and conductively doped poly and substrate regions which are simultaneously doped with the same impurity.

REFERENCES:
patent: 4127931 (1978-12-01), Shiba
patent: 4138782 (1979-02-01), Dela Moneda
patent: 4192059 (1980-03-01), Khan et al.
patent: 4246044 (1981-01-01), Yanase
patent: 4282648 (1981-08-01), Yu et al.
patent: 4341009 (1982-07-01), Bartholomew et al.

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