Radiation imagery chemistry: process – composition – or product th – Radiation modifying product or process of making – Radiation mask
Reexamination Certificate
1999-09-30
2001-11-27
Rosasco, S. (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Radiation modifying product or process of making
Radiation mask
Reexamination Certificate
active
06322934
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductors, and, more particularly, to a method for making integrated circuits on a semiconductor wafer.
BACKGROUND OF THE INVENTION
Integrated circuits are widely used in electronic devices, such as computers, cellular telephones, entertainment systems, etc. A typical integrated circuit includes a semiconductor substrate with a plurality of active regions formed therein. These active regions may be interconnected by various conductive or metal lines formed in layers on the substrate. Accordingly, an integrated circuit may include millions of transistors, for example.
As the densities of integrated circuits are continually increased, each feature, such as the width of a metal line, or the width of a polygate oxide layer, is continually reduced. Smaller features permit faster operation, less power consumption and more complicated functions to be performed. Such features are typically defined by selective exposure of a photoresist layer on a semiconductor wafer to a pattern imaged from a mask or reticle in a process generally known as optical lithography or photolithography. The exposed photoresist layer portions may be made etch resistant upon exposure to the image, for example. The non-exposed portions may then be removed leaving the desired photoresist pattern. The chemistry of the photoresist may also provide that exposed portions are etched and non-exposed portions remain. The remaining resist portions are then typically used to provide selective etching of the underlying integrated circuit portions.
The resolution and hence minimum feature size is related to the wavelength of light used in the photolithography. The so-called Rayleigh resolution criteria will soon define the limit of physics for imaging the ever-shrinking feature size in integrated circuit manufacturing. Continuing developments have allowed optical lithography to keep pace with decreasing feature sizes. As noted in the IEEE Spectrum article “Ultralight lithography” appearing at pp. 35-40, in July 1999, the lifetime of a given lithography generation is modified until a complete change to a next generation technology is made. In other words, various corrective measures are taken to help pattern smaller features, and which is limited by the wavelength of light used. Typical corrective techniques include optical proximity correction (OPC) and the use of phase-shift masks. Unfortunately, such phase-shift masks and OPC masks can be relatively expensive.
One possible alternative is to use successive printing or exposure steps, wherein a shift is performed between successive exposures as disclosed in U.S. Pat. Nos. 5,905,020 to Hu et al. and 5,811,222 to Gardner et al., for example. The Hu et al. patent in particular recognizes that to achieve a precise critical dimension, it was necessary to adjust the magnitude of the positional shift to account for process factors, such as the contrast of the photoresist and the degree of photoresist swelling during development. This compensation factor for a given process is described as being empirically determined based upon the critical dimension sought. In most cases this compensation factor fell within a range of 0.8 to 1.8.
Unfortunately, as circuit feature sizes are yet further reduced the overlap printing approach is useful, but may produce inaccurate features. This is so because only a constant scalar compensation factor is used. In many applications, the constant scalar compensation factor produces unacceptable results.
SUMMARY OF THE INVENTION
In view of the foregoing background, it is therefore an object of the present invention to provide a method for making integrated circuits having smaller feature sizes.
It is another object of the invention to provide a method for making integrated circuits having smaller feature sizes, based upon the overlap or shifted exposure approach and while accurately producing the small circuit features.
These and other objects, features and advantages in accordance with the present invention are provided by a method for making an integrated circuit on a semiconductor wafer, where the integrated circuit includes circuit features having a desired, relatively small, critical dimension. The method preferably comprises the steps of: designing a reticle including pattern features having a critical dimension to form corresponding circuit features based upon overlap areas defined by a plurality of exposure steps with a shift therebetween so that the circuit features have the desired, relatively small, critical dimension. Moreover, the designing step preferably includes determining a scaling factor function for relating the critical dimension of the pattern features and the shift to the desired critical dimension of the circuit features and while taking into account that the scaling factor function is also a function of the shift. The method also preferably includes the steps of fabricating the reticle and using the reticle to make the integrated circuit on the semiconductor wafer based on the plurality of exposure steps. The present invention recognizes that the scaling factor is not a single number, but instead is a non-linear function which is also based upon the shift between exposure steps.
The step of determining preferably comprises empirically determining the scaling factor function. The scaling factor function is also typically a function of a photolithography tool using the reticle, the tool's settings and a photoresist on the semiconductor wafer. Of course, the photoresist layer is applied on the semiconductor wafer and the reticle is used to selectively expose the photoresist layer. After exposure portions of the photoresist layer are removed.
The invention is particularly advantageous where the integrated circuit includes circuit features for gates of at least some relatively fast MOS transistors. Such relatively small features have been made using a second phase shift reticle in the past. However, the present invention obviates the need for the second relatively expensive phase shift reticle and the additional processing steps for using the phase shift reticle. In other words, the integrated circuit may include circuit features for fast MOS transistors and slow MOS transistors, and wherein the reticle is used for both the fast and slow MOS transistors in accordance with the invention.
The integrated circuit preferably includes circuit features that are generally rectangular in shape or have a shape based on a combination of rectangles. For such features, the shift between exposing steps is preferably in a diagonal direction.
Another method aspect of the invention is for defining circuit features having a desired, relatively small, critical dimension on a semiconductor wafer. The method preferably comprises designing a reticle including pattern features having a critical dimension to form corresponding circuit features based upon overlap areas defined by a plurality of exposure steps with a shift therebetween so that the circuit features have the desired, relatively small, critical dimension. The designing step preferably includes empirically determining a scaling factor function for relating the critical dimension of the pattern features and the shift to the desired critical dimension of the circuit features and while taking into account that the scaling factor function is also a function of the shift. The method also preferably includes the steps of fabricating the reticle, coating the semiconductor wafer with a layer of photoresist, and using the reticle for the plurality of exposure steps with the shift therebetween.
Yet another method aspect of the invention is directed to a method for designing a reticle. The reticle includes pattern features having a critical dimension to form corresponding circuit features in an integrated circuit on a semiconductor wafer based upon overlap areas defined by a plurality of exposure steps with a shift therebetween so that the circuit features have desired, relatively small, critical dimension. This method preferabl
Cuthbert John David
Jin Feng
Lucent Technologies - Inc.
Rosasco S.
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