Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Utility Patent
1999-07-30
2001-01-02
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S253000, C438S254000, C438S238000, C438S239000, C438S381000, C438S396000, C438S397000, C438S399000, C257S306000
Utility Patent
active
06169010
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor devices, and, more particularly, to a method for making a capacitor.
BACKGROUND OF THE INVENTION
Capacitors are used extensively in electronic devices for storing an electric charge. A capacitor includes two conductive plates or electrodes separated by an insulator. The capacitance, or amount of charge held by the capacitor per applied voltage, depends upon the area of the plates, the distance between them, and the dielectric value of the insulator. Capacitors may be formed within a semiconductor device, such as, for example, a dynamic random access memory (DRAM) or an embedded DRAM.
As semiconductor memory devices become more highly integrated, the area occupied by the capacitor of a DRAM storage cell shrinks, thus decreasing the capacitance of the capacitor because of its smaller electrode surface area. However, a relatively large capacitance is desired to prevent loss of stored information. Therefore, it is desirable to reduce the cell dimension and yet obtain a high capacitance, which achieves both high cell integration and reliable operation.
One technique for increasing the capacitance while maintaining the high integration of the storage cells is directed toward the shape of the capacitor electrodes. In this technique, the polysilicon layer of the capacitor electrodes may have protrusions, fins, cavities, etc., to increase the surface area of the capacitor electrode, thereby increasing its capacitance while maintaining the small area occupied on the substrate surface.
Instead of forming the capacitor on the substrate surface, capacitors are also formed above the substrate, i.e., they are stacked above the substrate. The surface area of the substrate can then be used for forming transistors. With respect to increasing the capacitance of a stack capacitor, U.S. Pat. No. 5,903,493 to Lee discloses a capacitor formed above a tungsten plug. The surface area of the capacitor is increased by etching a trench in the dielectric layer around the tungsten plug. The tungsten plug interfaces with an underlying interconnection line, thus allowing different layers formed above the substrate to be connected.
The trench is patterned by conventional etching or other suitable techniques. The fundamental limit on how far the trench can be etched is determined by how well the tungsten plug is anchored or secured within the dielectric layer. Typically, the depth of the trench is limited to about one half the thickness of the dielectric layer. After the trench has been etched, a capacitor is formed above the tungsten plug. Unfortunately, if the trench is etched beyond one half the thickness of the dielectric, the tungsten plug is more likely to become loose and fall out. This physical separation between the tungsten plug and the underlying metal interconnection with the interconnection line can cause open circuits to be formed resulting in complete failure of the device or circuit incorporating the capacitor.
SUMMARY OF THE INVENTION
In view of the foregoing background, it is therefore an object of the present invention to provide a method for making a capacitor having an increased capacitance without reducing the reliability thereof.
This and other advantages, features and objects in accordance with the present invention are provided by a method for making an integrated circuit capacitor including an anchored metal plug. More particularly, the method comprises the steps of forming an interconnection line adjacent a substrate, forming a first dielectric layer on the interconnection line, forming a first opening in the first dielectric layer, and forming a second opening in the interconnection line aligned with the first opening and having an enlarged width portion greater than a width of the first opening. The method further comprises filling the first and second openings with a conductive metal to define a metal plug having a body portion and an anchor portion adjacent lower portions of the first dielectric layer. The body portion and the anchor portion are preferably formed as a monolithic unit.
Because the metal plug is anchored, a depth of the trench can be greater without the metal plug becoming loose and separating from the underlying interconnection line. If this were to occur, an open circuit would occur resulting in failure of the device or circuit incorporating the integrated circuit capacitor. The anchor portion of the metal plug thus allows the depth of trench to be increased to thereby increase the capacitance, and without reducing the reliability of the integrated circuit capacitor.
The method also preferably includes forming a trench in the first dielectric layer adjacent the body portion of the metal plug, forming a first electrode lining the trench and contacting the metal plug, forming a second dielectric layer on the first electrode, and forming a second electrode on the second dielectric layer. Increasing the depth of the trench in accordance with the present invention increases the surface area of the first and second electrodes. This advantageously increases the capacitance of the capacitor, which is desired for preventing a loss of stored information.
REFERENCES:
patent: 4507852 (1985-04-01), Karulkar
patent: 4714686 (1987-12-01), Sander et al.
patent: 4879257 (1989-11-01), Patrick
patent: 5312775 (1994-05-01), Fujii et al.
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patent: 5619071 (1997-04-01), Myers et al.
patent: 5854105 (1998-12-01), Tseng
patent: 5854734 (1998-12-01), Sandhu et al.
patent: 5903493 (1999-05-01), Lee
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Keshavan Belur
Lucent Technologies - Inc.
Smith Matthew
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