Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1997-08-18
1998-09-01
Dang, Trung
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438433, 438428, 438782, 148DIG50, H01L 2176
Patent
active
058010823
ABSTRACT:
A method is achieved for making improved shallow trench isolation (STI) regions surrounding and electrically isolating device areas on a substrate using dielectric studs, spin-on-glass (SOG), and an isotropic wet etchback. The method consists of forming trenches in a silicon substrate using a pad oxide and silicon nitride mask. A thermal oxide is grown in the silicon trenches and a CVD silicon oxide is deposited and chemical/mechanically polished back to the silicon nitride masking layer to form dielectric studs (or plugs) in the silicon trenches that extend above the silicon substrate surface. The silicon nitride is removed in hot phosphoric acid, and a thin SOG is deposited to form disposable sidewall spacers on the raised studs. The thin SOG and the pad oxide are wet etched in HF acid to the device areas while isotropically etching back the disposable SOG sidewall spacers and dielectric studs to form shallow trench isolation regions having a raised convex surface. This eliminates dishing in the STI (concave STI) that results in undesirable variation in FET threshold voltage (V.sub.th). The gradual convex profile also minimizes the polysilicon residue problem when anisotropically etching the gate electrodes over the device areas. The use of SOG with wet etchback is more cost effective than the conventional CVD oxide deposition and plasma etchback process.
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Ackerman Stephen B.
Dang Trung
Saile George O.
Vanguard International Semiconductor Corporation
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