Method for making improved shallow trench isolation with dielect

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

438433, 438428, 438782, 148DIG50, H01L 2176

Patent

active

058010823

ABSTRACT:
A method is achieved for making improved shallow trench isolation (STI) regions surrounding and electrically isolating device areas on a substrate using dielectric studs, spin-on-glass (SOG), and an isotropic wet etchback. The method consists of forming trenches in a silicon substrate using a pad oxide and silicon nitride mask. A thermal oxide is grown in the silicon trenches and a CVD silicon oxide is deposited and chemical/mechanically polished back to the silicon nitride masking layer to form dielectric studs (or plugs) in the silicon trenches that extend above the silicon substrate surface. The silicon nitride is removed in hot phosphoric acid, and a thin SOG is deposited to form disposable sidewall spacers on the raised studs. The thin SOG and the pad oxide are wet etched in HF acid to the device areas while isotropically etching back the disposable SOG sidewall spacers and dielectric studs to form shallow trench isolation regions having a raised convex surface. This eliminates dishing in the STI (concave STI) that results in undesirable variation in FET threshold voltage (V.sub.th). The gradual convex profile also minimizes the polysilicon residue problem when anisotropically etching the gate electrodes over the device areas. The use of SOG with wet etchback is more cost effective than the conventional CVD oxide deposition and plasma etchback process.

REFERENCES:
patent: 5372968 (1994-12-01), Lur et al.
patent: 5506168 (1996-04-01), Morita et al.
patent: 5518950 (1996-05-01), Ibok et al.
patent: 5728621 (1998-03-01), Zheng et al.
patent: 5731241 (1998-03-01), Jang et al.
P.C. Fazan et al. "A Highly Manufacturable Trench Isolation Process for Deep Submicron DRAMs" in Proceedings of the International Electronic Device Meeting 1993, pp. 57-60. (No Month).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method for making improved shallow trench isolation with dielect does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for making improved shallow trench isolation with dielect, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for making improved shallow trench isolation with dielect will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-269821

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.