Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2000-03-13
2001-11-06
Bowers, Charles (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S533000, C257S536000, C257S532000
Reexamination Certificate
active
06313516
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of high-resistance polysilicon resistors for integrated circuits on semiconductor substrates, and more particularly relates to a two-layer polysilicon resistor structure that can have any desirable sheet resistance and have more reliable contacts than conventional polysilicon resistors.
(2) Description of the Prior Art
Many integrated circuits utilize both analog and digital circuits on the same chip, commonly referred to as mixed-mode circuits. Besides analog-to-digital converters (ADC) and digital-to-analog converters (DAC), some special applications circuits include audio Digital-Sign-Processing (DSP) circuits, battery chargers and the like. These mixed-mode circuits require capacitors and resistors having high resistance. These high value resistors are fabricated by patterning a doped polysilicon layer having high sheet resistivity R
S
that is expressed by the equation
R
S
=rho/T
where rho is the resistivity expressed in units of ohm-cm, and T is the thickness of the doped polysilicon expressed in cm. To achieve a high R
S
, it is therefore necessary to either increase the resistivity, rho, or to decrease the thickness, T. One method of doping the polysilicon layer is by POCl
3
doping, but the high resistivity values are difficult to control. Another method of achieving high sheet resistance R
S
is to use ion implantation, which more accurately controls the dopant level in the polysilicon layer. However, implanted resistors generally have greater variations in resistance as a function of temperature and voltage, typically expressed by the temperature coefficient of resistivity (TCR), and by the voltage coefficient of resistivity (VCR), respectively. Another method of increasing the resistance R
S
is to reduce the thickness T of the doped polysilicon layer. However, when the thickness of the polysilicon layer is reduced to less than 1000 Angstroms to increase the resistivity, contacts etched in an insulating layer over and to this thin polysilicon layer can result in overetching. Overetching of this thin polysilicon layer can damage the thin underlying interpolysilicon oxide (IPO) layer when the resistors are formed over the IPO layer, which also serves as the interelectrode dielectric for capacitors.
Several methods for making polysilicon resistors which are stable from hydrogen intrusion have been reported. For example, Hsu et al., U.S. Pat. No. 5,530,418, teach a method of forming a metal shield around a polysilicon resistor to prevent hydrogen intrusion. Another method for stabilizing polysilicon resistors from hydrogen intrusion is described by Chang et al. in U.S. Pat. No. 5,837,592, in which the polysilicon resistors are treated in a nitrogen plasma, which minimizes variations of the resistance due to hydrogen intrusion. Also, a method for making Static Random Access Memory (SRAM) with low stand-by currents is described by Wu et al., U.S. Pat. No. 5,728,598, in which the voltage on one polysilicon layer induces a depletion region in a second polysilicon layer that results in a higher sheet resistance.
However, there is still a need in the semi-conductor industry to provide polysilicon resistors having repeatable high resistance for mixed-mode circuit applications.
SUMMARY OF THE INVENTION
A principal object of this invention is to fabricate a resistor having high-value resistance that can be varied over a wide range of resistance values for use in analog/digital circuit applications.
It is another object of this invention to form these high-value resistors using two layers: a thin doped polysilicon layer for providing high sheet resistance, and an undoped polysilicon layer on the doped polysilicon layer for etching reliable contacts without destroying a thinner capacitor oxide under the doped polysilicon layer.
Still another objective of this invention is to integrate these resistors into the semiconductor process to provide a very manufacturable process.
In accordance with the objects of the invention, a method for fabricating improved polysilicon resistors having high sheet resistance for integrated circuits is described. The method and structure can be integrated with polycide FETs without significantly increasing processing complexity. These high-value polysilicon resistors can be formed by reducing the thickness of the doped polysilicon layer to less than 1000 Angstroms. However, when these polysilicon resistors are formed over capacitor bottom electrodes formed from the FET polycide layer, etching contact openings in an insulating layer to the thin doped polysilicon resistor can damage (overetch) the underlying thin interelectrode dielectric layer on the capacitor bottom electrodes.
The method for making these polysilicon resistors begins by providing a semiconductor substrate. Field oxide regions formed, for example by the local oxidation of silicon (LOCOS) method, surround and electrically isolate device areas for the FETs. A thin gate oxide is grown on the device areas for the FETs. A polycide layer, composed of a doped first polysilicon layer and an upper refractory metal silicide layer, is deposited and patterned to form FET gate electrodes over the device areas and to serve as local interconnections and the capacitor bottom electrodes over the field oxide-areas. Lightly doped source/drain areas are implanted in the device areas adjacent to the FET gate electrodes to minimize short-channel effects. Sidewall spacers are formed on the sidewalls of the gate electrodes, and source/drain contact areas are implanted to complete the FETs. The polysilicon resistors are now made by depositing a thin first insulating layer to form an interpolysilicon oxide (IPO) layer. This IPO layer is used as an inter-electrode dielectric layer for the capacitors, and typically is silicon oxide (SiO
2
) and usually is very thin (100 Angstroms or less) to provide high capacitance. A second polysilicon layer is deposited and is in-situ doped with phosphorus and is used to form the high-value resistors. The second polysilicon layer is deposited by low-pressure chemical vapor deposition (LPCVD) using silane (SiH
4
) and a dopant gas such as phosphine (PH
3
). The flow rate of the PH
3
can be adjusted to achieve different resistivities. To further increase the sheet resistance (R
S
), which is equal to the resistivity divided by the thickness of the polysilicon layer, the thickness of the polysilicon layer can be reduced. However, for mixed analog/digital circuits, which require high sheet resistance (for example 200-2000 ohms per square), the doped polysilicon layer may be thinner than 1000 Angstroms, and the contact openings etched in the insulator to this thin polysilicon layer can result in overetch that damages the thin underlying interelectrode dielectric layer. To circumvent this problem, the invention utilizes an undoped third polysilicon layer on the thin doped second polysilicon layer. The undoped third and thin doped second polysilicon layers are patterned to form resistors and concurrently to form top plates for capacitors. The resistor consists of the two layers that form parallel resistors between the contacts, but since the undoped polysilicon has a very high resistivity (essentially infinite), the resistance is determined predominantly by the thin doped second polysilicon layer. A relatively thick second insulating layer is deposited to electrically insulate the FET devices on the substrate, and include the capacitors and resistors. Contact openings for the resistors are etched in the second insulating layer and into the undoped third polysilicon layer to the doped second polysilicon layer, wherein the undoped third polysilicon layer prevents etching through the doped second polysilicon layer and overetching the thin first insulating layer on the polycide layer that is also used to form capacitor bottom electrodes. Electrically conducting plugs are formed in the contact openings. Preferably the plugs are formed by depositing a tungsten layer and chemicall
Chang Wen-Cheng
Tsui Yu-Ming
Yu Shung-Jen
Ackerman Stephen B.
Bowers Charles
Brewster William M.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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