Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Patent
1998-10-13
1999-06-29
Kunemund, Robert
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
438696, 438637, 438724, H01L 2132, C25D 1104
Patent
active
059168234
ABSTRACT:
A method for forming a dual damascene structure on a substrate is disclosed. The method comprises the steps of: forming a liner oxide layer onto the substrate; forming a first low k dielectric layer atop the liner oxide layer; forming a cap oxide layer atop the first low k dielectric layer; forming a first nitride layer atop the cap oxide layer; patterning and etching the first nitride layer to form a contact opening; forming a second low k dielectric layer into the contact opening and atop the first nitride layer; forming a second nitride layer atop the second low k dielectric layer; forming a photoresist layer atop the second nitride layer; patterning and developing the photoresist layer to expose a trench opening, wherein the trench opening is of different dimension than the contact opening; forming a dual damascene opening by etching the second nitride layer and the second low k dielectric layer, using the photoresist layer as a mask, and by etching the cap oxide layer, the first low k dielectric layer and the liner oxide layer, using the first nitride layer as a mask; stripping the photoresist layer; forming oxide sidewall spacers into the dual damascene opening; and depositing a conductive layer into the dual damascene opening.
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Lou Chine-Gie
Tu Yeur-Luen
Kunemund Robert
Okoro Bernadine
Worldwide Semiconductor Manufacturing Corporation
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