Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to conductive state
Patent
1996-08-20
1999-05-04
Niebling, John F.
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to conductive state
438600, 438467, H01L 2182
Patent
active
058997075
ABSTRACT:
An antifuse structure and method for making the antifuse structure having a doped antifuse layer is disclosed. The doped antifuse layer is preferably deposited over a lower electrode. A barrier layer may then be formed over the doped antifuse layer and an upper electrode may subsequently be deposited over the barrier layer. The method of depositing the doped antifuse layer includes: (a) providing a chemical vapor deposition reactor having a support chuck for supporting a partially fabricated silicon wafer; (b) powering up the chemical vapor deposition reactor and heating the partially fabricated silicon wafer; (c) selecting a dopant species for the antifuse layer (e.g, n-type or p-type); (d) introducing a gaseous mixture of a silane compound and the selected dopant species into the chemical vapor deposition reactor with the aid of a neutral species; and (e) depositing the antifuse layer over the lower electrode. When the antifuse structure is programmed, a wider conduction path is formed in the doped antifuse layer and deprogrammed states are prevented.
REFERENCES:
patent: 4174521 (1979-11-01), Neale
patent: 4420766 (1983-12-01), Kasten
patent: 4441167 (1984-04-01), Principi
patent: 4538167 (1985-08-01), Yoshino et al.
patent: 4569120 (1986-02-01), Stacy et al.
patent: 4569121 (1986-02-01), Lim et al.
patent: 5070384 (1991-12-01), McCollum et al.
patent: 5095362 (1992-03-01), Roesner
patent: 5106773 (1992-04-01), Chen et al.
patent: 5120679 (1992-06-01), Boardman et al.
patent: 5191241 (1993-03-01), McCollum et al.
patent: 5210598 (1993-05-01), Nakazaki et al.
patent: 5233206 (1993-08-01), Lee et al.
patent: 5248632 (1993-09-01), Tung et al.
patent: 5258891 (1993-11-01), Sako
patent: 5266829 (1993-11-01), Hamdy et al.
patent: 5272666 (1993-12-01), Tsang et al.
patent: 5290734 (1994-03-01), Boardman et al.
patent: 5293133 (1994-03-01), Birkner et al.
patent: 5300456 (1994-04-01), Tigelaar et al.
patent: 5328868 (1994-07-01), Conti et al.
patent: 5329153 (1994-07-01), Dixit
patent: 5373169 (1994-12-01), McCollum et al.
patent: 5381035 (1995-01-01), Chen et al.
patent: 5464790 (1995-11-01), Hawley
patent: 5482884 (1996-01-01), McCollum et al.
patent: 5489796 (1996-02-01), Harward
patent: 5493144 (1996-02-01), Bryant et al.
patent: 5493146 (1996-02-01), Pramanik et al.
patent: 5502315 (1996-03-01), Chua et al.
patent: 5557136 (1996-09-01), Gordon et al.
patent: 5593920 (1997-01-01), Haslam et al.
K.E. Gordon and R.J. Wong, "Conducting Filament of the Programmed Metal Electrode Amorphous Silicon Antifuse," QuickLogic Corp., Santa Clara, CA, 1993 IEEE, International Electron Devices Meeting, Dec. 5-8, 1993, Washington, DC.
Unknown, "Developments in non-volatile FPGAs," Electronic Engineering, Apr. 1993.
Sanchez Ivan
Vines Landon B.
Gurley Lynne A.
Niebling John F.
VLSI Technology Inc.
LandOfFree
Method for making doped antifuse structures does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for making doped antifuse structures, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for making doped antifuse structures will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1865117