Method for making bipolar/CMOS IC with isolated vertical PNP

Details Method for making bipolar/CMOS IC with isolated vertical PNP Method for making bipolar/CMOS IC with isolated vertical PNP

1990-07-16

1991-03-19

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 34, 437 56, 437 58, 148DIG9, 357 43, H01L 21331, H01L 21336

Patent

active

050010735

ABSTRACT:
The manufacture of an integrated circuit including an isolated vertical PNP, an isolated vertical NPN and isolated CMOS transistors is described. The PNP transistor has a shallow densely doped emitter made simultaneously with the source and drain of the PMOS transistor. The PNP base is made simultaneously with lightly doped portions of the LDD source and drain of the NMOS transistor. The PNP collector is made simultaneously with the P-well in which the NMOS transistor is formed. A P-buried layer in the isolated vertical PNP transistor provides a low collector resistance and is formed simultaneously with the P-buried layer of the NMOS transistor that extends the P-well there and better isolates the NMOS transistor from the substrate. And the N-buried layer providing superior isolation of the PNP with respect to the substrate is formed simultaneously with the N-buried layer of the vertical NPN transistor. All four of these transistors provide and are well suited for use in analog signal handling circuits. All are capable of operating at up to 15 volts. And both bipolar transistors have a high gain bandwidth.

REFERENCES:
patent: 4752589 (1988-06-01), Schaber
patent: 4830973 (1989-05-01), Mastroianni
patent: 4868135 (1989-09-01), Ogura et al.
patent: 4918026 (1990-04-01), Kosiak et al.
patent: 4954456 (1990-09-01), Kim et al.
Chiu, T. Y. et al., IEEE Electron Device Letters, vol. 11, No. 2, Feb. 1990, pp. 85-86.
Brassington, M. P. et al., IEEE Transactions on Electron Devices, vol. 36, No. 4, Apr. 1989, pp. 712-719.

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